Public Version
McBSP Functional Description
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As an example of how the McBSP module behaves in a transmit multichannel selection mode, suppose
that XMCM = 0b01 (all channels disabled unless individually enabled) and that you have enabled only
channels 0, 15, and 39. Suppose also that the frame length is 40. The McBSP module:
1. Shifts data to the mcbspi_dx pin in channel 0
2. Places the mcbspi_dx pin in the high impedance state in channels 1–14
3. Shifts data to the mcbspi_dx pin in channel 15
4. Places the mcbspi_dx pin in the high impedance state in channels 16–38
5. Shifts data to the mcbspi_dx pin in channel 39
21.4.6.7.1 Disabling/Enabling Versus Masking/Unmasking
For transmission, a channel can be:
•
Enabled and unmasked (transmission can begin and can be completed)
•
Enabled but masked (transmission can begin but cannot be completed)
•
Disabled (transmission cannot occur)
The definitions in
explain the channel control options:
Table 21-23. McBSP Channel Control Options
Enabled channel
A channel that can begin transmission by passing data from the data transmit register
(McBSPi.
) to the XSR through XB.
Masked channel
A channel that cannot complete transmission. The mcbspi_dx pin is held in the high impedance state; data
cannot be shifted out on the mcbspi_dx pin. In systems where symmetric transmit and receive provide software
benefits, this feature allows transmit channels to be disabled on a shared serial bus. A similar feature is not
needed for reception because multiple receptions cannot cause serial bus contention.
Disabled channel
A channel that is not enabled. A disabled channel is also masked. Because no DXR–to–XB copy occurs, the
McBSPi.
[1] XRDY bit is not set. Therefore, no DMA synchronization event is
generated, and if the transmit interrupt mode depends on XRDY (McBSPi.
XINTM=00b), no interrupt is generated. The McBSPi.
[2] XEMPTY bit is not affected.
Unmasked channel
A channel that is not masked. Data in the XSR(s) is shifted out on the mcbspi_dx pin.
21.4.6.7.2 Activity on McBSP Pins for Different Values of XMCM
shows the activity on the McBSP pins for the various McBSPi.
XMCM values. In all cases, the transmit frame is configured as follows:
•
XPHASE=0: Single–phase frame (required for multichannel selection modes)
•
XFRLEN1=0b0000011: 4 words per frame
•
XWDLEN1=0b000: 8 bits per word
•
XMCME=0: 2–partition mode (only partitions A and B used)
In the case where McBSPi.
[1:0] XMCM=0b11, transmission and reception are
symmetric, which means the corresponding bits for the receiver (RPHASE, RFRLEN1, RWDLEN1, and
RMCME) must have the same values as XPHASE, XFRLEN1, and XWDLEN1, respectively.
In
, the arrows showing where the various events occur are only sample indications.
Wherever possible, there is a time window in which these events can occur.
3118
Multi-Channel Buffered Serial Port
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
