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HS I
2
C Basic Programming Model
1. Test for arbitration lost (the I2Ci.
[0] AL "status" bit) and resolve accordingly.
2. Test for no acknowledgment (the I2Ci.
[1] NACK "status" bit) and resolve accordingly.
3. Test for register access ready (the I2Ci.
[2] ARDY "status" bit) and resolve accordingly.
4. Test for receive data ready (the I2Ci.
[3] RRDY "status" bit) and resolve accordingly.
5. Test for transmit data ready (the I2Ci.
[4] XRDY "status" bit) and resolve accordingly.
6. Test for general call (the I2Ci.
[5] GC "status" bit) and resolve accordingly.
7. Test for start (S) condition (the I2Ci.
[6] STC "status" bit) and resolve accordingly. For this
test, the functional clock must be inactive.
8. Test for access error (the I2Ci.
[7] AERR "status" bit) and resolve accordingly.
9. Test for bus free (the I2Ci.
[8] BF "status" bit) and resolve accordingly.
17.5.1.3 HS I
2
C Programming Flow Diagrams (I
2
C Mode)
through
are procedure flow charts for programming the I
2
C F/S and HS modes.
2801
SWPU177N – December 2009 – Revised November 2010
Multimaster High-Speed I
2
C Controller
Copyright © 2009–2010, Texas Instruments Incorporated