Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 2810 / 3738

Start
Yes
No
No
Yes
Clear RDR bit
(See Note 1)
Read
I2C .I2C_STAT i
register and save
value
Receive and
transfer ended
(RDR=1)?
bit = 1?
bit = 1?
Transmit
(XRDY=1)?
Is
interrupt received?
Yes
No
I2C .I2C_STAT[4] XRDY i
I2C .I2C_STAT[13] RDR
i
Read I2C .I2C_DATA register i
for I2C .I2C_BUFSTAT[13:8] i
RXSTAT times
Write I2C .I2C_DATA
i
register
No
Clear RRDY bit
(See Note 1)
Yes
Receive
(RRDY =1)?
bit = 1?
I2C .I2C_STAT[3] RRDY i
Read I2C .I2C_DATA register i
for I2C .I2C_BUF[13:8]
i
RTRSH + 1 times (See Note 2)
Clear ARDY bit
(See Note 1)
Yes
Can update
registers
(ARDY = 1)?
I2C .I2C_STAT[2]
ARDY bit = 1?
i
i2c-036
No
Clear XRDY bit
(See Note 1)
Public Version
HS I
2
C Basic Programming Model
www.ti.com
Figure 17-36. HS I
2
C Slave Transmitter/Receiver Mode, Interrupt (I
2
C Mode)
(1) The XRDY, RDR, RRDY, and ARDY bits are cleared by writing 1 to each corresponding bit in the
I2Ci.
I2C_STAT register.
(2) In slave transmitter mode, the amount of data requested by the external master I
2
C device is unknown; thus,
the I2Ci. I2C_BUF [5:0] XTRSH bit field must be configured to 0x0 (TX threshold = 1).
17.5.2 HS I
2
C Controller Basic Programming Model in SCCB Mode
This section describes the programming model of the multimaster HS I
2
C controllers configured in SCCB
mode.
17.5.2.1 HS I
2
C Main Program (SCCB Mode)
17.5.2.1.1 HS I
2
C Configure the Module Before Enabling the I
2
C Controller (SCCB Mode)
Before enabling the I
2
C controller, perform the following steps:
1. Enable the functional and interface clocks (see Section 17.3.1.1.1 , HS I
2
C Module Clocks).
2. Program the prescaler to obtain an approximately 12-MHz internal sampling clock (the
I2Ci_INTERNAL_CLK) by programming the corresponding value in the I2Ci. I2C_PSC [7:0] PSC bit
field. This value depends on the frequency of the functional clock (the I2Ci_FCLK). Because this
frequency is 96 MHz, the value of I2Ci.
I2C_PSC [7:0] PSC bit field is 0x7.
3. Program the I2Ci. I2C_SCLL [7:0] SCLL and I2Ci. I2C_SCLH [7:0] SCLH bit fields to obtain a bit rate of
100 Kbps (maximum authorized bit rate in SCCB mode). This value depends on the internal sampling
clock frequency (see
Table 17-12 ).
4. Configure the 7-bit slave address (ID value) by storing it in the I2Ci. I2C_SA register.
2810 SWPU177N – December 2009 – Revised November 2010
Multimaster High-Speed I
2
C Controller
Copyright © 2009–2010, Texas Instruments Incorporated