Texas Instruments OMAP36 Series, Technical Reference Manual

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HS I
2
C Register Manual
Bits Field Name Description Type Reset
0x1: Arbitration Lost interrupt enabled
Table 17-20. Register Call Summary for Register I2C_IE
HS I2C Integration
• HS I2C Interrupt Requests : [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16]
HS I2C Functional Description
• HS I2C Receive Mode in I2C Mode : [17]
• HS I2C FIFO Interrupt Mode Operation : [18]
• HS I2C FIFO Polling Mode Operation : [19] [20]
• HS I2C Draining Feature (I2C Mode Only) : [21] [22]
HS I2C Basic Programming Model
• HS I2C Main Program (I2C Mode) : [23] [24] [25] [26] [27] [28] [29] [30] [31] [32] [33] [34]
• HS I2C Main Program (SCCB Mode) : [35] [36] [37] [38] [39] [40] [41]
HS I2C Register Manual
• HS I2C Register Summary : [42]
Table 17-21. I2C_STAT
Address Offset 0x08
Physical Address 0x4806 0008 Instance I2C3
0x4807 0008 I2C1
0x4807 2008 I2C2
Description I
2
C status register. This register provides specific status information about the module, including
interrupt status information
Type RW
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XDR RDR BB ROVR XUDF AAS BF AERR STC GC XRDY RRDY ARDY NACK AL
RESERVED
Bits Field Name Description Type Reset
15 RESERVED Write 0s for future compatibility. Read returns 0. RW 0
14 XDR Transmit Draining IRQ status RW 0
Read Transmit draining inactive
0x0:
Read Transmit draining active
0x1:
Write No effect
0x0:
Write Clear this bit to 0
0x1:
13 RDR Receive Draining IRQ status RW 0
Read Receive draining inactive
0x0:
Read Receive draining active
0x1:
Write No effect
0x0:
Write Clear this bit to 0
0x1:
12 BB Bus busy status. Read-only bit. Writing this bit does not R 0
affect the read value.
2821 SWPU177N – December 2009 – Revised November 2010
Multimaster High-Speed I
2
C Controller
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