Public Version
HS I
2
C Basic Programming Model
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17.5.1.1.3 HS I
2
C Configure Slave Address and the Data Control Register (I
2
C Mode)
In master mode, configure the slave address register by programming the I2Ci.
[9:0] SA bit field
and the number of data bytes (I
2
C data payload) associated with the transfer by programming the
I2Ci.
[15:0] DCOUNT bit field.
NOTE:
For a 10-bit address, set the I2Ci.
[8] XSA bit to 1.
17.5.1.1.4 HS I
2
C Initiate a Transfer (I
2
C Mode)
Poll the I2Ci.
[12] BB bit. If it is cleared to 0 (bus not busy), configure the I2Ci.
[0] STT
and I2Ci.
[1] STP bits. To initiate a transfer, the I2Ci.
[0] STT bit must be set to 1, and it
is not mandatory to set the I2Ci.
[1] STP bit to 1.
17.5.1.1.5 HS I
2
C Receive Data (I
2
C Mode)
Poll the I2Ci.
[3] RRDY bit, or use the RRDY interrupt (the I2Ci.
[3] RRDY_IE bit must be
set to 1) or the DMA RX channel (the I2Ci.
[15] RDMA_EN bit must be set to 1) to read the
receive data in the I2Ci.
register.
If the transfer length does not equal the RX FIFO threshold (the I2Ci.
[13:8] RTRSH bit field + 1),
use the draining feature (enable the RDR interrupt by setting the I2Ci.
[13] RDR_IE bit to 1).
NOTE:
In receive mode only, the I2Ci.
[11] ROVR (receive overrun) bit indicates whether
the receiver has experienced overrun. An overrun condition occurs when the shift register
and the RX FIFO are full. An overrun condition does not result in data loss; the I
2
C controller
simply holds the serial clock line i2ci_scl to low to prevent other bytes from being received.
The I2Ci.
[7] AERR bit is set to 1 when a read access is performed in the
I2Ci.
register while the RX FIFO is empty. The corresponding interrupt can be
enabled by setting the I2Ci.
[7] AERR_IE bit to 1.
17.5.1.1.6 HS I
2
C Transmit Data (I
2
C Mode)
Poll the I2Ci.
[4] XRDY bit, or use the XRDY interrupt (the I2Ci.
[4] XRDY_IE bit must be
set to 1) or the DMA TX channel (the I2Ci.
[7] XDMA_EN bit must be set to 1) to write data to the
I2Ci.
register.
If the transfer length does not equal the TX FIFO threshold (the I2Ci.
[5:0] XTRSH bit field + 1),
use the draining feature (enable the XDR interrupt by setting the I2Ci.
[14] XDR_IE bit to 1).
NOTE:
In transmit mode only, the I2Ci.
[10] XUDF bit indicates whether the transmitter
has experienced underflow.
In master transmit mode, underflow occurs when the shift register and the TX FIFO are
empty and there are still some bytes to transmit (the I2Ci.
[15:0] DCOUNT bit field
value is not 0).
In slave transmit mode, underflow occurs when the shift register and the TX FIFO are empty
and the external I
2
C master device still requests data bytes to be read.
The I2Ci.
[7] AERR bit is set to 1 when a write access is performed in the
I2Ci.
register while the TX FIFO is full. The corresponding interrupt can be
enabled by setting the I2Ci.
[7] AERR_IE bit to 1.
Underflow interrupt on the FIFO can be also enabled from the I2Ci.
[10] XUDF_IE bit.
17.5.1.2 HS I
2
C Interrupt Subroutine Sequence (I
2
C Mode)
Perform the following steps:
2800
SWPU177N – December 2009 – Revised November 2010
Multimaster High-Speed I
2
C Controller
Copyright © 2009–2010, Texas Instruments Incorporated
