Texas Instruments OMAP36 Series, Technical Reference Manual

Page: 2828 / 3738

Public Version
HS I
2
C Register Manual
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Table 17-30. Register Call Summary for Register I2C_CNT
HS I2C Integration
• HS I2C Interrupt Requests : [0] [1] [2] [3]
HS I2C Functional Description
• HS I2C Transmit Mode in I2C Mode : [4]
• HS I2C Draining Feature (I2C Mode Only) : [5]
HS I2C Basic Programming Model
• HS I2C Main Program (I2C Mode) : [6] [7]
• HS I2C Programming Flow Diagrams (I2C Mode) : [8] [9] [10] [11] [12] [13]
HS I2C Register Manual
• HS I2C Register Summary : [14]
Table 17-31. I2C_DATA
Address Offset 0x1C
Physical Address 0x4806 001C Instance I2C3
0x4807 001C I2C1
0x4807 201C I2C2
Description This register is the end point/entry point for the LH to read data from or write data to the FIFO
buffer.
Read accesses from an empty FIFO (i.e. at reset) or write accesses to a full FIFO will return
error.
Type RW
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved DATA
Bits Field Name Description Type Reset
15:8 Reserved Write 0s for future compatibility. Read returns 0. RW 0x00
7:0 DATA Transmit/Receive FIFO data RW 0x–
Table 17-32. Register Call Summary for Register I2C_DATA
HS I2C Integration
• HS I2C DMA Requests : [0] [1] [2] [3] [4] [5]
• HS I2C Interrupt Requests : [6] [7]
HS I2C Functional Description
• HS I2C Transmit Mode in I2C Mode : [8]
• HS I2C Receive Mode in I2C Mode : [9] [10]
• HS I2C System Test Mode : [11] [12]
• HS I2C Write and Read Operations in SCCB Mode : [13] [14]
HS I2C Basic Programming Model
• HS I2C Main Program (I2C Mode) : [15] [16] [17] [18]
• HS I2C Main Program (SCCB Mode) : [19] [20]
HS I2C Register Manual
• HS I2C Register Summary : [21]
2828 SWPU177N – December 2009 – Revised November 2010
Multimaster High-Speed I
2
C Controller
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