Texas Instruments OMAP36 Series, Technical Reference Manual

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Public Version
HS I
2
C Integration
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Table 17-9. HS I
2
C Interrupt Events
Event Supported Status Bit Mask Bit This Event Happens When:
Name Configuration
Mode
AL event I
2
C mode only I2Ci. I2C_STAT [0] AL I2Ci. I2C_IE [0] Two or more I
2
C master devices initiate a transfer and the
AL_IE I
2
C module I2Ci in the device loses arbitration of the I
2
C
bus.
NACK I
2
C mode only I2Ci. I2C_STAT [1] I2Ci. I2C_IE [1] A nonacknowledgment has been received. In master mode,
event NACK NACK_IE the transfer is automatically ended by generating a stop
condition on the bus. The I2Ci.
I2C_CON [1] STP,
I2Ci. I2C_CON [10] MST, and I2Ci. I2C_CON [9] TRX bits are
automatically cleared to 0 (slave receiver mode). TX and
RX FIFOs must be cleared (the I2Ci.
I2C_BUF [6]
TXFIFO_CLR and I2Ci. I2C_BUF [14] RXFIFO_CLR bits are
set to 1).
ARDY I
2
C and SCCB I2Ci. I2C_STAT [2] I2Ci. I2C_IE [2] One of the following cases occurs:
event modes ARDY ARDY_IE
• In I
2
C master receiver mode, the I2Ci. I2C_CON [1]
STP bit is set to 1, the I2Ci. I2C_CNT [15:0] DCOUNT
bit field value is 0, and the RX FIFO is empty.
• In I
2
C master transmitter mode, the I2Ci. I2C_CON [1]
STP bit is set to 1 and the I2Ci. I2C_CNT [15:0]
DCOUNT bit field value is 0.
• In I
2
C master transmitter mode, the I2Ci. I2C_CON [1]
STP bit is cleared to 0 and the I2Ci. I2C_CNT [15:0]
DCOUNT bit field value passed 0.
• In I
2
C master receiver mode, the I2Ci. I2C_CON [1]
STP bit is set to 1, the I2Ci. I2C_CNT [15:0] DCOUNT
field value passed 0, and the RX FIFO is empty.
• In I
2
C slave transmitter mode, a stop(P) or start (S)
condition is received from the external I
2
C master
device.
• In I
2
C slave receiver mode, a stop(P) or start (S)
condition is received from the external I
2
C master
device and the RX FIFO is empty.
• In SCCB master transmitter or receiver mode, a stop
(P) condition is detected.
RRDY I
2
C receive I2Ci. I2C_STAT [3] I2Ci. I2C_IE [3] The RX FIFO level is above the threshold
event mode and RRDY RRDY_IE (I2Ci. I2C_BUF [13:8] RTRSH bit field value + 1).
SCCB read
mode
XRDY I
2
C transmit I2Ci. I2C_STAT [4] I2Ci. I2C_IE [4] The module requires new data to be served. A master
event mode and XRDY XRDY_IE transmitter module requests new data when the TX FIFO
SCCB write level is below the threshold (I2Ci. I2C_BUF [5:0] XTRSH bit
mode field value + 1) and the required amount of data to be
transmitted specified by the I2Ci.
I2C_BUFSTAT [5:0]
TXSTAT bit field is greater than the threshold. A slave
transmitter requests new data when the TX FIFO is below
the threshold (if the I2Ci.
I2C_BUF [5:0] XTRSH bit field
value is greater than 1), or when there is a read request
from the external master device (for each acknowledge
received from the master) when the I2Ci.
I2C_BUF [5:0]
XTRSH bit field value is 1.
GC event I
2
C mode only I2Ci. I2C_STAT [5] GC I2Ci. I2C_IE [5] The module detects a general call on the I
2
C bus (all bits of
GC_IE the address cleared to 0).
STC I
2
C mode only I2Ci. I2C_STAT [6] I2Ci. I2C_IE [6] The module is in idle mode and a start (S) condition is
event STC STC_IE asynchronously detected on the I
2
C bus and signaled with
a wakeup. When the active mode is restored and the
interrupt generated, this bit indicates the reason for the
wakeup.
(1)
.
(1)
The interrupt request generation on an STC event must be enabled only if the module is configured to allow the possibility of
switching off the functional clock while in IDLE state (the I2Ci.I2C_SYSC[9:8] CLOCKACTIVITY bit field set to b00 or b01). The
first transfer (corresponding to the detected start [S] condition) is lost, and is used only to restore the active mode of the module.
On the I
2
C bus, the external master that generated the transfer detects this behavior as a nonacknowledge to the address phase
and may possibly restart the transfer.
2788 SWPU177N – December 2009 – Revised November 2010
Multimaster High-Speed I
2
C Controller
Copyright © 2009–2010, Texas Instruments Incorporated