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HS I
2
C Basic Programming Model
5. Configure the 8-bit register address (subaddress) by storing it in the I2Ci.
register.
6. Configure the I2Ci.
[13:8] RTRSH bit field to 0x0 (RX threshold to 1) and the
I2Ci.
[5:0] XTRSH bit field to 0x0 (TX threshold to 1).
7. Take the I
2
C controller out of reset by setting the I2Ci.
[15] I2C_EN bit to 1.
17.5.2.1.2 HS I
2
C Initialize the I
2
C Controller (SCCB Mode)
To initialize the I
2
C controller, perform the following steps:
1. Configure the I2Ci.
register:
•
In SCCB mode, only the master mode is supported; set the I2Ci.
[10] MST bit to 1.
•
For transmitter mode (write to the external SCCB device register) or receiver mode (read from the
external SCCB device register), set the I2Ci.
[9] TRX bit (0: receiver; 1: transmitter).
2. If using an interrupt to transmit/receive data, set the corresponding bit in the I2Ci.
register to 1
(the I2Ci.
[4] XRDY_IE bit for the transmit interrupt, the I2Ci.
[3] RRDY bit for the receive
interrupt). Also, if needed enable the I2Ci.
[11] ROVR_IE bit for receiving start of draining on the
internal FIFO interrupt. If using the HS I
2
C for transmitter the I2Ci.
[10] XUDF_IE bit for
interrupting if underflow occurs on the internal FIFO.
17.5.2.1.3 HS I
2
C Initiate a Transfer (SCCB Mode)
Poll the I2Ci.
[12] BB bit. If it is cleared to 0 (bus not busy), set the I2Ci.
[0] STT bit to
1. Because a transfer allows the LH to write or read only a single byte to or from the external SCCB
device, the transmission automatically stops at the end of the transfer. When the transfer completes, the
I2Ci.
[2] ARDY bit is set to 1. In SCCB mode, the I2Ci.
[1] STP bit is not used.
17.5.2.1.4 HS I
2
C Receive Data (SCCB Mode)
Poll the I2Ci.
[3] RRDY bit, or use the RRDY interrupt (the I2Ci.
[3] RRDY_IE bit must be
set to 1) to read the receive data in the I2Ci.
register.
NOTE:
In SCCB mode, the I2Ci.
[13:8] RTRSH bit field (RX threshold) must be set to a
value of 0x0 (RX threshold = 1).
17.5.2.1.5 HS I
2
C Transmit Data (SCCB Mode)
Poll the I2Ci.
[4] XRDY bit, or use the XRDY interrupt (the I2Ci.
[4] XRDY_IE bit must be
set to 1) to write the data to the I2Ci.
register.
NOTE:
In SCCB mode, the I2Ci.
[5:0] XTRSH bit field (TX threshold) must be set to a
value of 0x0 (TX threshold = 1).
17.5.2.2 HS I
2
C Interrupt Subroutine Sequence (SCCB Mode)
Perform the following steps:
1. Test for register access ready (the I2Ci.
[2] ARDY status bit) and resolve accordingly.
2. Test for receive data ready (the I2Ci.
[3] RRDY status bit) and resolve accordingly.
3. Test for transmit data ready (the I2Ci.
[4] XRDY status bit) and resolve accordingly.
17.5.2.3 HS I
2
C Programming Flow Diagrams (SCCB Mode)
through
are procedure flow charts for programming the SCCB mode.
2811
SWPU177N – December 2009 – Revised November 2010
Multimaster High-Speed I
2
C Controller
Copyright © 2009–2010, Texas Instruments Incorporated
