Time
Bytes in TX FIFO
0
TX FIFO depth
(I2C .I2C_BUFSTAT[15:14]
i
FIFODEPTH bit field)
Active-low DMA TX request
I2C .I2C_BUF[5:0]
i
XTRSH bit field value + 1
i2c-025
Time
Bytes in TX FIFO
0
TX FIFO depth
(I2C .I2C_BUFSTAT[15:14]
i
FIFODEPTH bit field)
Active-low DMA TX request
I2C .I2C_BUF[5:0]
i
XTRSH bit field value +1
i2c-026
Public Version
HS I
2
C Functional Description
www.ti.com
In transmit mode, a DMA request is automatically asserted by the I2Ci_DMA_TX signal when the TX FIFO
is empty. This request is deasserted when the number of bytes (the I2Ci.
[5:0] XTRSH bitfield
value + 1) is written in the FIFO by the sDMA controller. If an insufficient number of bytes is written, the
DMA request remains active.
and
show the DMA TX transfers with different
values for the I2Ci.
[5:0] XTRSH bitfield.
Figure 17-25. HS I
2
C Transmit FIFO Request Generation (High Threshold)
Figure 17-26. HS I
2
C Transmit FIFO Request Generation (Low Threshold)
NOTE:
In SCCB mode, the RX and TX threshold values must be set to 1 by setting the
I2Ci.
[5:0] XTRSH bitfields to 0x0.
17.4.4.4 HS I
2
C Draining Feature (I
2
C Mode Only)
The draining feature is implemented to handle the end of a transfer whose length is not a multiple of the
FIFO threshold values (the I2Ci.
[13:8] RTRSH bitfield value + 1 for the RX threshold and the
I2Ci.
[5:0] XTRSH bitfield value + 1 for the TX threshold). It also offers the possibility of
transferring the remaining number of bytes (because the threshold is not reached).
This feature prevents the LH or the sDMA controller from trying more FIFO accesses than necessary (for
example, to generate at the end of a transfer a DMA RX request having fewer bytes in the FIFO than the
configured DMA transfer length). Otherwise, an AERR interrupt is generated by the I2Ci.
AERR bit.
2794
SWPU177N – December 2009 – Revised November 2010
Multimaster High-Speed I
2
C Controller
Copyright © 2009–2010, Texas Instruments Incorporated