Public Version
HS I
2
C Register Manual
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17.6 HS I
2
C Register Manual
CAUTION
The HS I2Ci registers are limited to 16 bit and 8 bit data accesses; 32–bit data
access is not allowed and can corrupt register content.
NOTE:
For register configuration of HS I
2
C controller I2C4, see
, Power, Reset, and Clock
Management.
provides the instance summary.
17.6.1 HS I
2
C Instance Summary
provides the instance summary.
Table 17-15. HS I
2
C Instance Summary
Module Name
Base Address
Size
HS I
2
C1
0x4807 0000
512 bytes
HS I
2
C2
0x4807 2000
512 bytes
HS I
2
C3
0x4806 0000
512 bytes
17.6.2 HS I
2
C Registers
17.6.2.1 HS I
2
C Register Summary
lists the I2Ci registers (where i = 1, 2 and 3).
Table 17-16. HS I
2
C Registers Mapping Summary
Register Name
Type
Register Width
Address Offset
Physical
Physical
Physical
(Bits)
Address for HS
Address for HS
Address for HS
I
2
C1
I
2
C2
I
2
C3
R
16
0x00
0x4807 0000
0x4807 2000
0x4806 0000
RW
16
0x04
0x4807 0004
0x4807 2004
0x4806 0004
RW
16
0x08
0x4807 0008
0x4807 2008
0x4806 0008
RW
16
0x0C
0x4807 000C
0x4807 200C
0x4806 000C
R
16
0x10
0x4807 0010
0x4807 2010
0x4806 0010
RW
16
0x14
0x4807 0014
0x4807 2014
0x4806 0014
RW
16
0x18
0x4807 0018
0x4807 2018
0x4806 0018
RW
16
0x1C
0x4807 001C
0x4807 201C
0x4806 001C
RW
16
0x20
0x4807 0020
0x4807 2020
0x4806 0020
RW
16
0x24
0x4807 0024
0x4807 2024
0x4806 0024
RW
16
0x28
0x4807 0028
0x4807 2028
0x4806 0028
RW
16
0x2C
0x4807 002C
0x4807 202C
0x4806 002C
RW
16
0x30
0x4807 0030
0x4807 2030
0x4806 0030
RW
16
0x34
0x4807 0034
0x4807 2034
0x4806 0034
RW
16
0x38
0x4807 0038
0x4807 2038
0x4806 0038
RW
16
0x3C
0x4807 003C
0x4807 203C
0x4806 003C
R
16
0x40
0x4807 0040
0x4807 2040
0x4806 0040
RW
16
0x44
0x4807 0044
0x4807 2044
0x4806 0044
RW
16
0x48
0x4807 0048
0x4807 2048
0x4806 0048
RW
16
0x4C
0x4807 004C
0x4807 204C
0x4806 004C
2818
SWPU177N – December 2009 – Revised November 2010
Multimaster High-Speed I
2
C Controller
Copyright © 2009–2010, Texas Instruments Incorporated