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HS I
2
C Register Manual
Table 17-33. I2C_SYSC
Address Offset
0x20
Physical Address
0x4806 0020
Instance
I2C3
0x4807 0020
I2C1
0x4807 2020
I2C2
Description
This register controls the various parameters of the L4-Core interconnect interface.
Type
RW
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
Е
SERVED
RESERVED
IDLEMODE
SRST
AUTOIDLE
ENAWAKEUP
CLOCKACTIVITY
Bits
Field Name
Description
Type
Reset
15:10
RESERVED
Write 0s for future compatibility. Read returns 0.
RW
0x00
9:8
CLOCKACTIVITY
Clock Activity selection bits
RW
0x0
0x0:
Both clocks can be cut off
0x1:
Only interface clock must be kept active;
functional clock can be cut off
0x2:
Only functional clock must be kept active;
interface clock can be cut off
0x3:
Both clocks must be kept active
7:5
RESERVED
Write 0s for future compatibility. Read returns 0.
RW
0x0
4:3
IDLEMODE
Idle Mode selection bits
RW
0x0
0x0:
Force Idle mode
0x1:
No Idle mode
0x2:
Smart Idle mode
0x3:
Reserved
2
ENAWAKEUP
Enable wakeup control bit
RW
0
0x0:
Wakeup mechanism is disabled
0x1:
Wakeup mechanism is enabled
1
SRST
Software reset. This bit is automatically reset by the
RWl
0
hardware. During reads, it always returns 0.
0x0:
Normal mode
0x1:
The module is reset
0
AUTOIDLE
Auto Idle enable control bit
RW
1
0x0:
Auto Idle mechanism is disabled
0x1:
Auto Idle mechanism is enabled
Table 17-34. Register Call Summary for Register I2C_SYSC
HS I2C Integration
•
[0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10]
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:
HS I2C Register Manual
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2829
SWPU177N – December 2009 – Revised November 2010
Multimaster High-Speed I
2
C Controller
Copyright © 2009–2010, Texas Instruments Incorporated
