Public Version
HS I
2
C Integration
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Each HS I
2
C controller can be configured through the I2Ci.
[4:3] IDLEMODE bit field as one of
the following acknowledgment modes:
•
Force-idle mode (I2Ci.
[4:3] IDLEMODE bit field = b00): The module immediately enters idle
mode when a low-power-mode request is received from the PRCM module. In this mode, software
must ensure that there are no asserted output interrupts before requesting this mode to go to IDLE
state.
•
No-idle mode (I2Ci.
[4:3] IDLEMODE bit field = b01): The module never enters idle mode.
•
Smart-idle mode (I2Ci.
[4:3] IDLEMODE bit field = b10): After receiving a low-power-mode
request from the PRCM module, the module enters idle mode only after all asserted output interrupts
are acknowledged and there is no pending internal event.
NOTE:
The value I2Ci.
[4:3] IDLEMODE = b11 must not be used.
describes the HS I
2
C controller power-management modes.
Table 17-4. HS I
2
C Power Management Modes
Power-Management Mode Requested by the PRCM
I2Ci.
[4:3] IDLEMODE Bit Field Value (where i = 1, 2, 3)
Module
Force-idle
b00
No-idle
b01
Smart-idle
b10
Reserved (not used)
b11
The PRCM module gates the interface and/or the functional clocks after receiving the acknowledgment of
the I2Ci (where i = 1, 2, 3). The I2Ci.
[9:8] CLOCKACTIVITY bit field indicates the state of the
interface and functional clocks of the module when in idle mode.
lists the value of the
I2Ci.
[9:8] CLOCKACTIVITY bit field and indicates the state of the interface and functional
clocks at the PRCM clock generator output in idle mode.
Table 17-5. HS I
2
C State of the Interface and Functional Clocks When the Module is in Idle Mode
I2Ci.
Functional Clock
Interface Clock
CLOCKACTIVITY Bit Field
Value (where i= 1, 2, 3)
b00
Off
Off
b01
Off
On
b10
On
Off
b11
On
On
NOTE:
The PRCM.CM_AUTOIDLE1_CORE[15] AUTO_I2C1, PRCM.CM_AUTOIDLE1_CORE[16]
AUTO_I2C2, and PRCM.CM_AUTOIDLE1[17] AUTO_I2C3 bits control, for each HS I
2
C
controller, whether the L4-Core interconnect interface clock is enabled or disabled in
synchronization with the CORE power domain state transition (see
, Power, Reset,
and Clock Management).
NOTE:
The voltage controller, in which HS I
2
C controller I2C4 is implemented, has no idle
request/acknowledge mechanism. The idle modes for the voltage controller are directly
managed by the PRM module. For details, see
, Power, Reset, and Clock
Management.
17.3.1.2.3 HS I
2
C Wake-Up Capability
Each HS I
2
C controller can wake up the system by generating a wake-up request through the I2Ci_WAKE
signal connected to the PRCM module.
2784
SWPU177N – December 2009 – Revised November 2010
Multimaster High-Speed I
2
C Controller
Copyright © 2009–2010, Texas Instruments Incorporated
