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HS I
2
C Integration
•
PRCM.CM_ICLKEN1_CORE[15] EN_I2C1 bit for I2C1
•
PRCM.CM_ICLKEN1_CORE[16] EN_I2C2 bit for I2C2
•
PRCM.CM_ICLKEN1_CORE[17] EN_I2C3 bit for I2C3
The functional clock can be enabled or disabled for each multimaster HS I
2
C controller by setting the
following bits in the PRCM module:
•
PRCM.CM_FCLKEN1_CORE[15] EN_I2C1 bit for I2C1
•
PRCM.CM_FCLKEN1_CORE[16] EN_I2C2 bit for I2C2
•
PRCM.CM_FCLKEN1_CORE[17] EN_I2C3 bit for I2C3
The functional clock is processed by a prescaler block to produce the internal sampling clock. This clock is
generated by the I
2
C prescaler block. The prescaler block consists of the I2Ci.
[7:0] PSC bit field
(where i = 1, 2, 3) that is used to divide down the functional clock to obtain an internal sampling clock with
a frequency value of I2Ci_FCLK/(I2Ci.
[7:0] PSC bit field value + 1, where i = 1, 2, 3).
NOTE:
The I2C4.
[7:0] PSC bit field of I2C4 is not accessible by software. For details
about the bit rates available for I2C4, see
, HS I
2
C Clocking.
17.3.1.2 HS I
2
C Power Management
17.3.1.2.1 HS I
2
C Module Power Saving
This section describes power-saving techniques for the HS I
2
C controllers. To conserve power, when no
activity is detected on the L4-Core interconnect interface of the module, each of these modules supports
an automatic idle mode that is enabled or disabled by setting the I2Ci.
[0] AUTOIDLE bit.
When this bit is asserted (set to 1), if no activity is detected on the L4-Core interface, automatic idle mode
is enabled and the interface clock I2Ci_ICLK is disabled internally to the module, thus reducing power
consumption.
When new activity is detected on the L4-Core interconnect interface of the module, the clock restarts with
no latency penalty. After reset, automatic idle mode is disabled; thus, this mode must be enabled by
software for reduced power consumption.
17.3.1.2.2 HS I
2
C System Power Management
As part of the system-wide power-management scheme, each HS I
2
C controller supports a communication
protocol with the PRCM module to request the module to enter a low-power mode. When a module
acknowledges a low-power mode request from the PRCM module, the interface and/or the functional
clocks are gated off at the PRCM clock generator. Because the clocks are disabled at the source, the
low-power mode offers lower power consumption than the internal clock autogating method used by local
power management.
The PRCM.CM_ICLKEN1_CORE[15] EN_I2C1, PRCM.CM_ICLKEN1_CORE[16] EN_I2C2, and
PRCM.CM_ICLKEN1_CORE[17] EN_I2C3 bits in the PRCM module control the interface clocks of the HS
I
2
C1, I
2
C2, and I
2
C3 modules, respectively.
The PRCM.CM_FCLKEN1_CORE[15] EN_I2C1, PRCM.CM_FCLKEN1_CORE[16] EN_I2C2, and
PRCM.CM_FCLKEN1_CORE[17] EN_I2C3 bits in the PRCM module control the functional clocks of the
HS I
2
C1, I
2
C2, and I
2
C3 modules, respectively.
For details about clock enabling and disabling in the PRCM module, see
, Power, Reset, and
Clock Management.
2783
SWPU177N – December 2009 – Revised November 2010
Multimaster High-Speed I
2
C Controller
Copyright © 2009–2010, Texas Instruments Incorporated