Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 2806 / 3738

Start
No
Yes
End
Clear XDR bit
(see Note 1)
Read
I2C .I2C_STAT i
register
Is bus
free?
Write I2C .I2C_CON with 8403h or 8401h i
(F/S mode) or with 9403h or 9401h (HS
mode)
Read I2C .I2C_STAT i
register and save
value
I2C .I2C_STAT[1] i
NACK bit = 0?
No
No No
No
Yes
Yes
Yes
Yes
Yes
Is ACK
returned
(NACK=0)?
Is
arbitration
lost (AL=1)?
Can
update the
registers
(ARDY=1)?
I2C .I2C_STAT[0] AL i
bit = 1?
I2C .I2C_STAT[2] i
ARDY bit = 1?
I2C .I2C_STAT[13] i
RDR bit = 1?
I2C .I2C_STAT[3] i
RRDY bit = 1?
Is
last data received
at end of transfer
(RDR=1)?
Is
enough data
received
(RRDY bit=1)?
Decisions
based on the
saved value of
I2C .I2C_STAT
i
register
Read I2Cn.I2C_DATA
register for
I2Cn.I2C_BUF[13:8]
RTRSH + 1 times
Clear RRDY bit
(see Note 1)
No
[EXPECTED COMMAND SEQUENCE]
- Full transfer
(I2C .I2C_CON[0] STT bit; I2Cn.I2C_CON[1] STP bit) = (1;1)
i
- 2 phases transfer
(I2C .I2C_CON[0] STT bit; I2C .I2C_CON[1] STP bit) = (1:0), and then (0;1)
i i
- Multiple phases transfer
(I2C .I2C_CON[0] STT bit; I2C .I2C_CON[1] STP bit) = (1;0), (1;0)....and then (0;1) or (1;1)
i i
[EXPECTED I2C_IE] I2C .I2C_IE = 200Fh i
Read I2C .I2C_BUFSTAT[13:8] i
RXSTAT to check the amount of
data left to be received
Clear ARDY bit
(see Note 1)
Clear AL bit
(see Note 1)
Clear NACK bit
(see Note 1)
Read I2C .I2C_DATA i
register for
I2C .I2C_BUFSTAT[13:8] i
RXSTAT times
I2C .I2C_CON[0] STT and i
I2C .I2C_CON[1] STP and i
I2C .I2C_CON[10] MST bits i
are cleared by hardware
I2C .I2C_CON[0] STT and i
I2C .I2C_CON[1] STP bits i
are cleared by hardware
Reprogram the
registers
(see Note 2)
New start?
Yes
No
Hardware releases the serial
clock line (i2ci_scl) to high
I C controller goes into
2
slave receiver mode.
Stop?
Yes
Yes
No
Is
interrupt
received?
Set appropriate value to every bit of I2C .12C_CON register. i
I2C .I2C_CON[15] I2C_EN bit must be set to 1 to take the I C controller i
2
out of reset.
Setting this bit and setting other mode bits can be done simultaneously.
I2C .I2C_STAT[12] BB bit = 0? i
No
i2c-032
Public Version
HS I
2
C Basic Programming Model
www.ti.com
Figure 17-32. HS I
2
C Master Receiver Mode, Interrupt Method, in F/S and HS Modes (I
2
C Mode)
(1) The NACK, AL, ARDY, RDR, and RRDY bits are cleared by writing 1 to each corresponding bit in the
I2Ci.
I2C_STAT register.
(2) Reprogram registers means: I2Ci. I2C_CON [11] STB and/or I2Ci. I2C_CON [10] MST bit and/or
I2Ci. I2C_SA [9:0] SA register and/or I2Ci. I2C_CNT [15:0] DCOUNT register and/or I2Ci. I2C_CON [0] STT bit
and/or I2Ci. I2C_CON [1] STP bit.
2806 SWPU177N – December 2009 – Revised November 2010
Multimaster High-Speed I
2
C Controller
Copyright © 2009–2010, Texas Instruments Incorporated