Texas Instruments OMAP36 Series, Technical Reference Manual

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HS I
2
C Basic Programming Model
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can be set to 1 when the I2Ci. I2C_SYSTEST [11] SSB bit is set to 1. Clearing the I2Ci. I2C_SYSTEST [11]
SSB bit to 0 does not clear the I2Ci. I2C_STAT [5:0] status bits to 0. The I2Ci. I2C_STAT [5:0] status bits
can be cleared to 0 only by writing 1 in the corresponding bits. In addition to the test modes, this actual
data can be polled to see what is being inputted and outputted on the two clock and data lines. These
tests are only available in functional mode.
Table 17-14 lists the data polling tests.
Table 17-14. HS I
2
C List of Data In/Out Checks
I2Ci. I2C_SYSTEST Test Description
Bit Field
[8] SCL_I_FUNC SCL line input value Testing/reading incoming 1 or 0 on the clock line
[7] SCL_O_FUNC SCL line output value Testing/reading outgoing 1 or 0 on the clock line
[6] SDA_I_FUNC SDA line input value Testing/reading incoming 1 or 0 on the data line
[5] SDA_O_FUNC SDA line output value Testing/reading outgoing 1 or 0 on the data line
17.4.10 HS I
2
C Write and Read Operations in SCCB Mode
In SCCB mode, the HS I
2
C controller can write or read a single byte to or from the external SCCB device.
To write a single byte to the external SCCB device, the HS I
2
C controller must be configured in
multimaster transmitter mode by setting the I2Ci. I2C_CON [10] MST and I2Ci. I2C_CON [9] TRX bits to 1.
The external device slave address (7-bit address of the ID value) is set in the I2Ci. I2C_SA register; the
register address (8-bit subaddress in the external SCCB device) is set in the I2Ci.I2C_OA register. The
8-bit data to be transmitted is written by the LH in the I2Ci.
I2C_DATA register.
To read a single byte from the external SCCB device, the HS I
2
C controller must be configured in
multimaster receiver mode by setting the I2Ci. I2C_CON [10] MST to 1 and by clearing the
I2Ci. I2C_CON [9] TRX bit to 0. The external device slave address (7-bit address of the ID value) is set in
the I2Ci. I2C_SA register; the register address (8-bit subaddress in the external SCCB device) is set in the
I2Ci.I2C_OA register. The 8-bit data received from the external SCCB device is read by the LH from the
I2Ci.
I2C_DATA register.
NOTE: In SCCB mode, the RX and TX thresholds must be set to 1 by configuring the
I2Ci. I2C_BUF [13:8] RTRSH and I2Ci. I2C_BUF [5:0] XTRSH bit fields to 0x0.
17.4.11 HS I
2
C Power Chip Communication Operations
The master transmitter HS I
2
C controller I2C4 inside the voltage controller of the PRM module is used to
send configuration commands from the LH to external power chip(s).
For voltage control operations, the LH must set the slave address of the first power chip in the
PRCM.PRM_VC_SMPS_SA[6:0] SA0 bit field, and the slave address of the second power chip (if
necessary) in the PRCM.PRM_VC_SMPS_SA[22:16] SA1 bit field.
The LH must also configure the specific registers in the voltage controller of the PRCM module, for the
voltage control and power-sequencing functions.
A high-priority bypass mode is available to allow the LH to configure the external power chip(s) through
the I
2
C bus. To write 8-bit data to the configuration registers of an external power chip, the LH must set
the 7-bit external power chip slave address in the PRCM.PRM_VC_BYPASS_VAL[6:0] SLAVEADDR bit
field, the configuration register address in the PRCM.PRM_VC_BYPASS_VAL[15:8] REGADDR bit field,
and the 8-bit data in the PRCM.PRM_BYPASS_VAL[23:16] bit field.
For details about voltage control, see Chapter 3 , Power, Reset, and Clock Management.
17.5 HS I
2
C Basic Programming Model
17.5.1 HS I
2
C Controller Basic Programming Model in I
2
C Mode
This section describes the programming model of the multimaster HS I
2
C controllers configured in I
2
C
mode.
2798 SWPU177N – December 2009 – Revised November 2010
Multimaster High-Speed I
2
C Controller
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