Time
Bytes in RX FIFO
0
RX FIFO depth
(I2C .I2C_BUFSTAT[15:14]
i
FIFODEPTH bit field)
Programmable threshold
(I2C .I2C_BUF[13:8] RTRSH
i
bit field value + 1)
Active-low DMA RX request
I2C .I2C_BUF[13:8]
i
RTRSH bit field value + 1
i2c-024
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HS I
2
C Functional Description
In interrupt mode, the module offers two options for the LH application to handle the interrupts:
•
When detecting an interrupt request (XRDY/RRDY type), the LH can write/read 1 data byte to/from the
TX/RX FIFO and then clear the interrupt. The module reasserts the interrupt until the interrupt
condition is no longer met.
•
When detecting an interrupt request (XRDY/RRDY type), the LH can be programmed to write/read the
number of data bytes specified by the corresponding FIFO threshold (the I2Ci.
[5:0] XTRSH
bitfield value + 1 for the TX threshold or the I2Ci.
[13:8] RTRSH bitfield value + 1 for the RX
threshold). In this case, the interrupt condition is cleared and the next interrupt is asserted again when
the XRDY/RRDY condition is met again.
If the second-interrupt-serving approach is used, an additional mechanism (draining feature) is
implemented for cases where the transfer length is not a multiple of the FIFO threshold value (see
, HS I
2
C Draining Feature (I
2
C Mode Only).
NOTE:
In slave transmit mode (the I2Ci.
[10] MST bit is cleared and the I2Ci.
TRX bit is set to 1), the draining feature must not be used, because the transfer length is not
known at configuration time, and the external master can end the transfer at any point by not
acknowledging 1 data byte. If the draining feature is used in slave transmit mode, data can
remain in the TX FIFO without being transmitted over the I
2
C bus. In this case, the TX FIFO
must be cleared by setting the I2Ci.
[6] TXFIFO_CLR bit.
17.4.4.2 HS I
2
C FIFO Polling Mode Operation
In FIFO polled mode (the I2Ci.
[4] XRDY_IE and I2Ci.
[3] RRDY_IE bits are disabled, and the
I2Ci.
[15] RDMA_EN and I2Ci.
[7] XDMA_EN bits are disabled), the status of the module
(receiver or transmitter) can be checked by polling the I2Ci.
[3]
RRDY bits (the I2Ci.
[14] XDR bits can also be polled if the
draining feature is enabled). The I2Ci.
[4] XRDY and I2Ci.
[3] RRDY bits accurately
reflect the interrupt conditions described in the discussion of the FIFO interrupt mode operation.
17.4.4.3 HS I
2
C FIFO DMA Mode Operation (I
2
C Mode Only)
In receive mode, a DMA request is generated by the I2Ci_DMA_RX signal as soon as the RX FIFO
exceeds its threshold level (the I2Ci.
[13:8] RTRSH bitfield value + 1). This request is deasserted
when the number of bytes defined by the threshold level is read by the sDMA controller.
shows the DMA request generation in receive mode.
Figure 17-24. HS I
2
C Receive FIFO DMA Request Generation
2793
SWPU177N – December 2009 – Revised November 2010
Multimaster High-Speed I
2
C Controller
Copyright © 2009–2010, Texas Instruments Incorporated
