Public Version
Display Subsystem Basic Programming Model
www.ti.com
To begin transmission, the protocol drives TXREQUESTHS high on a rising edge of TXByteClkHS. The
PHY detects this signal on the next rising edge, following which it initiates the LP Start of Transmission
(SoT) procedure.
During a high-speed Clock Transmission, these parameters are defined in multiples of CLKIN4DDR and
programmed by the following register bit fields:
•
TLPX timing is programmed by the DSS.
[20:16] REG_TLPXBY2 bit field.
•
THS-PREPARE
timing
is
programmed
by
the
DSS.
[31:24]
REG_THSPREPARE bit field.
•
TCLK-ZERO timing is programmed by the DSS.
[7:0] REG_TCLKZERO bit field.
TCLK-ZERO is extended, if required, so that the entire LP SoT procedure lasts an integer number of
TXByteClkHS cycles.
At the end of the SoT procedure, HS clock transmission begins. At the same time, TXREADYHS is made
high.
To stop clock transmission, the protocol drives TXREQUESTHS low on a rising edge of TXByteClkHS.
The DSI_PHY detects this change in TXREQUESTHS on the next edge and stops clock transmission.
TXREADYHS is made low.
The DSI_PHY then goes through the LP End of Transmission (EoT) procedure. TCLK-TRAIL and
THS-EXIT parameters are also multiples of CLKIN4DDR and programmed by the following register fields:
•
TCLK-TRAIL timing is programmed by the DSS.
[15:8] REG_TCLKTRAIL bit
field.
•
THS-EXIT timing is programmed by the DSS.
[7:0] REG_THSEXIT bit field.
The DSI_PHY completes the SoT and EoT procedures, once begun, irrespective of any change in PPI
signals. If TXREQUESTHS goes low during the SoT procedure, the PHY start the EoT procedure
immediately after finishing the SoT procedure and no clock is transmitted.
STOPSTATE is high whenever the line is in LP-11 state, as determined by the outputs of the Low Power
Receivers. This signal is not synchronized with TXByteClkHS.
It is requires that the high speed clock be present for some time before (TCLK-PRE) and some time after
(TCLK-POST) high speed data transmission. The protocol must ensure that these timings are met by
asserting and deasserting TXREQUESTHS appropriately.
The PHY ensures that the clock signal has a quadrature-phase with respect to a toggling bit sequence on
any Data Lane, and a rising edge in the center of the first transmitted bit of every Data byte. These
relations are not described in the timing diagram.
CLKIN4DDR can be shut off 300ns after the clock lane goes to STOPSTATE. Alternatively, CLKIN4DDR
can be shut down after TCLK-Trail + THS-Exit + 2 Txbyteclk periods after TxRequestHS falling edge is
received by DSI_PHY.
The DSI protocol engine must ensure that TXREQUESTESC, TXULPSCLK, and TURNREQUEST are low
whenever TXREQUESTHS is asserted.
7.5.6.4.2 High-Speed Data Transmission
shows an example of high-speed Data Transmission.
1760
Display Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
