Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 1952 / 3738

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Display Subsystem Register Manual
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Bits Field Name Description Type Reset
1 ECC_CORRECTION_ Virtual channel - ECC has been used to correct the only 1-bit RW 0x0
IRQ_EN error (short and long packet).
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
0 CS_IRQ_EN Virtual channel - Check-Sum of the payload mismatch RW 0x0
detection
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
Table 7-433. Register Call Summary for Register DSI_VCn_IRQENABLE
Display Subsystem Functional Description
• Command Mode : [0]
• Bus Turnaround : [1]
Display Subsystem Basic Programming Model
• Interrupts : [2]
• Command Mode Transfer Example 1 : [3]
• Command Mode Transfer Example 2 : [4]
Display Subsystem Register Manual
• DSI Protocol Engine Register Mapping Summary : [5]
7.7.2.6 DSI Complex I/O Registers
NOTE: Copyright 2005-2008 MIPI Alliance, Inc. All rights reserved. MIPI Alliance Member
Confidential.
Table 7-434. DSI_PHY_REGISTER0
Address Offset 0x0000 0000
Physical Address 0x4804 FE00 Instance DSI_PHY
Description Configuration register for HS mode timings
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REG_THSPREPARE REG_THSPRPR_THSZERO REG_THSTRAIL REG_THSEXIT
Bits Field Name Description Type Reset
31:24 REG_THSPREPARE REG_THSPREPARE timing parameter in multiples of DDR clock RW 0x1E
period. DDR clock = CLKIN4DDR/4.
D-PHY specification: 40 ns + 4*UI ÷ 85 ns + 6*UI.
UI = Unit Interval, equal to the duration of any HS state on the
clock lane
Actual value seen on line:
= REG_THSPREPARE timer + analog delay and slew on
signals
= REG_THSPREPARE * DDR_Clock_ (–26.5 ns --- +4
ns)
PROGRAMMED VALUE = ceil (70 ns / DDR_Clock_Period) + 2.
Default value is programmed for 400 MHz.
23:16 REG_THSPRPR_THSZE REG_THSPRPR_THSZERO timing parameter in multiples of RW 0x48
RO DDR clock period. DDR clock = CLKIN4DDR/4.
D-PHY specification: > 145 ns + 10*UI
Actual value seen on line:
1952 Display Subsystem SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated