Texas Instruments OMAP36 Series, Technical Reference Manual

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Display Subsystem Register Manual
Table 7-123. DSI Protocol Engine Register Mapping Summary (continued)
Register Name Type Register Width (Bits) Address Offset Physical Address
DSI_RX_FIFO_VC_SIZ RW 32 0x074 0x4804 FC74
E
DSI_COMPLEXIO_CFG RW 32 0x078 0x4804 FC78
2
DSI_RX_FIFO_VC_FUL R 32 0x07C 0x4804 FC7C
LNESS
DSI_VM_TIMING4 RW 32 0x080 0x4804 FC80
DSI_TX_FIFO_VC_EMP R 32 0x084 0x4804 FC84
TINESS
DSI_VM_TIMING5 RW 32 0x088 0x4804 FC88
DSI_VM_TIMING6 RW 32 0x08C 0x4804 FC8C
DSI_VM_TIMING7 RW 32 0x090 0x4804 FC90
DSI_STOPCLK_TIMING RW 32 0x094 0x4804 FC94
DSI_VCn_CTRL RW 32 0x100+ (n* 0x20)
(1)
0x4804 FD00+ (n*
0x20)
(1)
DSI_VCn_TE RW 32 0x104+ (n* 0x20)
(1)
0x4804 FD04+ (n*
0x20)
(1)
DSI_VCn_LONG_PACK W 32 0x108+ (n* 0x20)
(1)
0x4804 FD08+ (n*
ET_HEADER 0x20)
(1)
DSI_VCn_LONG_PACK W 32 0x10C+ (n* 0x20)
(1)
0x4804 FD0C+ (n*
ET_PAYLOAD 0x20)
(1)
DSI_VCn_SHORT_PAC RW 32 0x110+ (n* 0x20)
(1)
0x4804 FD10+ (n*
KET_HEADER 0x20)
(1)
DSI_VCn_IRQSTATUS RW 32 0x118+ (n* 0x20)
(1)
0x4804 FD18+ (n*
0x20)
(1)
DSI_VCn_IRQENABLE RW 32 0x11C+ (n* 0x20)
(1)
0x4804 FD1C+ (n*
0x20)
(1)
(1)
n = 0 to 3
7.7.1.8 DSI_PHY Register Mapping Summary
Table 7-124. DSI_PHY Register Mapping Summary
Register Name Type Register Width (Bits) Address Offset Physical Address
DSI_PHY_REGISTER0 RW 32 0x0000 0000 0x4804 FE00
DSI_PHY_REGISTER1 RW 32 0x0000 0004 0x4804 FE04
DSI_PHY_REGISTER2 RW 32 0x0000 0008 0x4804 FE08
DSI_PHY_REGISTER3 RW 32 0x0000 000C 0x4804 FE0C
DSI_PHY_REGISTER4 RW 32 0x0000 0010 0x4804 FE10
DSI_PHY_REGISTER5 R 32 0x0000 0014 0x4804 FE14
7.7.1.9 DSI PLL Controller Register Mapping Summary
Table 7-125. DSI PLL Controller Register Mapping Summary
Register Name Type Register Width (Bits) Address Offset Physical Address
DSI_PLL_CONTROL RW 32 0x0000 0000 0x4804 FF00
DSI_PLL_STATUS R 32 0x0000 0004 0x4804 FF04
DSI_PLL_GO RW 32 0x0000 0008 0x4804 FF08
DSI_PLL_CONFIGURA RW 32 0x0000 000C 0x4804 FF0C
TION1
DSI_PLL_CONFIGURA RW 32 0x0000 0010 0x4804 FF10
TION2
1817 SWPU177N – December 2009 – Revised November 2010 Display Subsystem
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