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Display Subsystem Register Manual
Bits
Field Name
Description
Type
Reset
Actual value seen on line:
N = REG_TCLKZERO
M = REG_TCLKPREPARE = {ceil [(N + 3)/4] * 4 + ceil(M/4) * 4 – M + 2} *
DDR_Clock_ (~ 0 ns --- +5 ns)
PROGRAMMED VALUE = ceil (265 ns / DDR_Clock_Period)
Default value is programmed for 400 MHz.
Table 7-437. Register Call Summary for Register DSI_PHY_REGISTER1
Display Subsystem Functional Description
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Timing Parameters for an LP to HS Transaction
:
•
Timing Parameters for an HS to LP Transaction
:
•
:
Display Subsystem Basic Programming Model
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:
•
•
Turn-Around Request in Transmit Mode
•
Turn-Around Request in Receive Mode
Display Subsystem Use Cases and Tips
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:
•
:
Display Subsystem Register Manual
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DSI_PHY Register Mapping Summary
Table 7-438. DSI_PHY_REGISTER2
Address Offset
0x0000 0008
Physical Address
0x4804 FE08
Instance
DSI_PHY
Description
Sync pattern and reserved bits
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
HSSYNCPATTERN
RESERVED
REG_TCLKPREPARE
Bits
Field Name
Description
Type
Reset
31:24
HSSYNCPATTERN
Default : 184 (10111000). MSB (last received bit of sync pattern),
RW
0xB8
LSB (first received bit of sync pattern).
23:8
RESERVED
Reserved. Read returns zero. Write only zero for future
R
0x0
compatibility.
7:0
REG_TCLKPREPARE REG_TCLKPREPARE timing parameter in multiples of DDR clock
RW
0x1A
period. DDR clock = CLKIN4DDR/4.
D-PHY specification: 38 ns ÷ 95 ns
Actual value seen on line:
= REG_TCLKPREPARE timer + analog delay and slew on LP
signals
= REG_TCLKPREPARE * DDR_Clock_ (~– 25 ns --- +5
ns)
PROGRAMMED VALUE = ceil (65 ns / DDR_Clock_Period)
Default value is programmed for 400 MHz.
1955
SWPU177N – December 2009 – Revised November 2010
Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated