Texas Instruments OMAP36 Series, Technical Reference Manual

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dss-325
CLK REQUEST
CLK READY
DATA REQUEST
CLK LANE
CLK STATE
LP
DATA LANE
DATA STATE
DATA READY
ZERO
ENTER
HS
DDR_CLK_PRE
CLK
ON
ZERO
ENTER
HS
HS
PACKET
T
LPX
T
CLK-PREPARE
T
CLK-ZERO
ENTER_HS_MODE_LATENCY
T
CLK-PRE
T
LPX
T
HS-PREPARE
T
HS-ZERO
LP
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Display Subsystem Functional Description
7.4.3.2.1 Timing Parameters for an LP to HS Transaction
Figure 7-89 shows the timing requirement when switching the data and clock lane state from LP to HS.
Table 7-31 lists the LP to HS timing parameters.
Figure 7-89. LP to HS Timing
Table 7-31. LP to HS Timing Parameters
Timing Description Register
Length of any low-power state period. The value set in
DSI_PHY_REGISTER1 [20:16]
T
LPX
DSI_PHY_REGISTER1 [20:16] REG_TLPXBY2 bit field
REG_TLPXBY2
is half of the T
LPX
.
Time to drive the CLK lane to LP-00 state, to prepare DSI_PHY_REGISTER2 [7:0]
T
CLK-PREPARE
for HS clock transmission REG_TCLKPREPARE
Time to drive the CLK lane to HS-0 state before DSI_PHY_REGISTER1 [7:0]
T
CLK-ZERO
starting the clock REG_TCLKZERO
Time that the HS clock must be driven before any
associated data lane begins the transition from LP to
T
CLK-PRE
HS mode T
CLK-PRE
= DDR_CLK_PRE - T
LPX
-
T
CLK-PREPARE
- T
CLK-ZERO
Time to drive the data lane to LP-00 state, to prepare DSI_PHY_REGISTER0 [31:24]
T
HS-PREPARE
for HS packet transmission REG_THSPREPARE
Time to drive the data lane to HS-0 state before the
synchronous sequence. T
HS-ZERO
= DSI_PHY_REGISTER0 [23:16]
T
HS-ZERO
DSI_PHY_REGISTER0 [23:16] REG_THSPRPR_THSZERO
REG_THSPRPR_THSZERO - T
HS-PREPARE
1661 SWPU177N – December 2009 – Revised November 2010 Display Subsystem
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