Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 1953 / 3738

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Display Subsystem Register Manual
Bits Field Name Description Type Reset
N = REG_THSPREPARE_THSZERO – REG_THSPREPARE
M = REG_THSPREPARE = {ceil[(N + 3)/4] * 4 + ceil(M/4) * 4 +
3} * DDR_Clock_ (~ – 29 ns --- 0 ns).
PROGRAMMED VALUE = ceil (175 ns / DDR_Clock_Period) +
2.
Default value is programmed for 400 MHz.
15:8 REG_THSTRAIL REG_THSTRAIL timing parameter in multiples of DDR clock RW 0x1D
period. DDR clock = CLKIN4DDR/4.
D-PHY specification: > 60 ns + 4*UI
Actual value seen on line:
N = REG_THSTRAIL = {ceil [(N + 3)/4] * 4 – 2.75} *
DDR_Clock_ (~ 0 ns --- 5 ns)
PROGRAMMED VALUE = ceil (60 ns / DDR_Clock_Period) + 5.
Default value is programmed for 400 MHz.
7:0 REG_THSEXIT REG_THSEXIT timing parameter in multiples of DDR clock RW 0x3A
period. DDR clock = CLKIN4DDR/4)
D-PHY specification: > 100 ns
Actual value seen on line:
N = REG_THSEXIT = THSEXIT timer + analog delay and slew
on LP signals = [ceil(N/4)*4] * DDR_Clock_Period – (~ 3 ns ---
45 ns)
PROGRAMMED VALUE = ceil (145 ns/ DDR_Clock_Period)
Default value is programmed for 400 MHz.
Table 7-435. Register Call Summary for Register DSI_PHY_REGISTER0
Display Subsystem Functional Description
• Timing Parameters for an LP to HS Transaction : [0] [1] [2]
• Timing Parameters for an HS to LP Transaction : [3] [4]
• Shadowing Register : [5]
Display Subsystem Basic Programming Model
• High-Speed Clock Transmission : [6] [7]
• High-Speed Data Transmission : [8] [9] [10]
Display Subsystem Use Cases and Tips
• Configure DSI_PHY : [11] [12] [13] [14]
• Configure DSI_PHY Timing : [15] [16] [17] [18]
Display Subsystem Register Manual
• DSI_PHY Register Mapping Summary : [19]
Table 7-436. DSI_PHY_REGISTER1
Address Offset 0x0000 0004
Physical Address 0x4804 FE04 Instance DSI_PHY
Description Configuration register for LP mode and HS mode timings
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REG_TLPXBY2 REG_TCLKTRAIL REG_TCLK_ZERO
RESERVED
REG_TTAGO
REG_TTAGET
REG_TTASURE
1953 SWPU177N – December 2009 – Revised November 2010 Display Subsystem
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