dss-E130
=
=
+
´
=
+
FHSB
FCLKIN4DDR /16
FVPP
FCLKIN4DDR /((Re gM3 1) DISPC _ LCD * DISPC _ PCD)
FVP
FCLKIN4DDR /(Re gM3 1)
dss-E131
=
´
+
+
+
=
´
´
+
+
+
TL
FHSB / FVPP (DISPC _ HSA
DISPC _ HFP PPL DISPC _ HBP)
TL1f
(BPP /(8 NDL)) (DISPC _ HSA
DISPC _ HFP PPL DISPC _ HBP)
dss-E132
+
+
+
´
=
+
+
+
+
´
+
=
´
+
+
+
-
+
+
=
´
+
+
+
(DISPC _ HSA
DISPC _ HBP PPL DISPC _ HFP) Fppi
(HS HBP ((WC
6) / NDL) HFP)
Fvp
HBP HFP
(TVPP / THSB) (DISPC _ HSA
DISPC _ HFP PPL DISPC _ HBP) (HS
(WC
6) / NDL))
HBPplusHFP
(FHSB / FVPP) (DISPC _ HSA
DISPC _ HFP PPL DISPC _ HBP)
-
+
+
=
´
+
+
+
-
+
+
=
´
´
-
=
-
(HS
WC
6) / NDL
HBPplusHFPf
((FHSB / FVPP) (DISPC _ HSA
DISPC _ HFP PPL DISPC _ HBP)) ((HS
WC
6) / NDL)
HFP
(DISPC _ HFP BPP) /(NDL 8) (2 / NDL)
HBP
HBPplusHFP HFP
Public Version
Display Subsystem Use Cases and Tips
www.ti.com
Table 7-107. DSI Timing Registers (continued)
Steps
Register/Bit Field/Programming
Value
Enable the ECC generation for the transmit
DSI_VC0_CTRL[8] ECC_TX_EN
0x1
header.
Enable high-speed mode to send short and
DSI_VC0_CTRL[9] MODE_SPEED
0x1
long packets to the peripheral.
Disable DMA request for TX FIFO.
DSI_VC0_CTRL[23:21] DMA_TX_REQ_NB
0x4
Disable DMA request for RX FIFO.
DSI_VC0_CTRL[29:27] DMA_RX_REQ_NB
0x4
Configuration TX and RX FIFO
Set size of the RX FIFO allocated for VC1 to
[15:12]
0x1
32 x 33 bits.
VC1_FIFO_SIZE
Set size of the TX and TX FIFO allocated for
[15:12]
0x3
VC1 to 96 x 33 bits.
VC1_FIFO_SIZE
•
Freq TxByteClkHS:
•
Length of the line in video mode in number of byte clock cycles (TxByteClkHS):
•
Blanking periods (HBP + HFP) in DSI are calculated based on the following formula:
7.6.5.1.2.5 Configure DSI_PHY Timing
summarizes DSI_PHY timing in the functions of DDR_CLK_P with DDR_CLK_P =
1000/DSI_DDR_CLK. For more details on timing calculation, see
, Clock Requirements.
Table 7-108. Configure DSI_PHY Timing
Steps
Register/Bit Field/Programming
Value
Settings of the DSI protocol timing. For a
complete description of timing
CEIL(70 ns/DDR clock period)
[31:24] REG_THSPREPARE
specifications, see
, Clock
+ 2
Requirements.
[23:16]
ceil(175 ns/DDR clock period)
REG_THSPRPR_THSZERO
+ 2
[7:0] REG_THSEXIT
ceil(145 ns/DDR clock period)
ceil(60 ns/DDR clock period) +
[15:8] REG_THSTRAIL
5
1808Display Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated