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Display Subsystem Register Manual
Bits
Field Name
Description
Type
Reset
26:24
VC3_FIFO_ADD
Address of the space allocated in the FIFO for VC 3. For a
RW
0x0
complete description, refer to
23:20
VC2_FIFO_SIZE
Size of the FIFO allocated for VC 2. For a complete description,
RW
0x0
refer to
19
RESERVED
Write 0s for future compatibility.
RW
0x0
Reads returns 0.
18:16
VC2_FIFO_ADD
Address of the space allocated in the FIFO for VC 2. For a
RW
0x0
complete description, refer to
15:12
VC1_FIFO_SIZE
Size of the FIFO allocated for VC 1. For a complete description,
RW
0x0
refer to
11
RESERVED
Write 0s for future compatibility.
RW
0x0
Reads returns 0.
10:8
VC1_FIFO_ADD
Address of the space allocated in the FIFO for VC 1.For a
RW
0x0
complete description, refer to
7:4
VC0_FIFO_SIZE
Size of the FIFO allocated for VC 0. For a complete description,
RW
0x0
refer to
3
RESERVED
Write 0s for future compatibility.
RW
0x0
Reads returns 0.
2:0
VC0_FIFO_ADD
Address of the space allocated in the FIFO for VC 0. For a
RW
0x0
complete description, refer to
Table 7-401. Register Call Summary for Register DSI_TX_FIFO_VC_SIZE
Display Subsystem Basic Programming Model
•
:
Display Subsystem Use Cases and Tips
•
Display Subsystem Register Manual
•
DSI Protocol Engine Register Mapping Summary
Table 7-402. DSI_RX_FIFO_VC_SIZE
Address Offset
0x0000 0074
Physical Address
0x4804 FC74
Instance
DSI_PROTOCOL_ENGINE
Description
Defines the corresponding memory entries allocated for each VC and the addresses. The VC must be
disabled to allocate/un-allocate some entries in the RX FIFO.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
RESERVED
RESERVED
RESERVED
VC3_FIFO_ADD
VC2_FIFO_ADD
VC1_FIFO_ADD
VC0_FIFO_ADD
VC3_FIFO_SIZE
VC2_FIFO_SIZE
VC1_FIFO_SIZE
VC0_FIFO_SIZE
Bits
Field Name
Description
Type
Reset
31:28
VC3_FIFO_SIZE
Size of the FIFO allocated for VC 3. For a complete description,
RW
0x0
refer to
27
RESERVED
Write 0s for future compatibility.
RW
0x0
Reads returns 0.
26:24
VC3_FIFO_ADD
Address of the space allocated in the FIFO for VC 3.For a
RW
0x0
complete description, refer to
23:20
VC2_FIFO_SIZE
Size of the FIFO allocated for VC 2. For a complete description,
RW
0x0
refer to
19
RESERVED
Write 0s for future compatibility.
RW
0x0
Reads returns 0.
1935
SWPU177N – December 2009 – Revised November 2010
Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated