Texas Instruments OMAP36 Series, Technical Reference Manual

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Display Subsystem Register Manual
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Table 7-122. Video Encoder Register Mapping Summary (continued)
Register Name Type Register Width Address Offset Physical Address
(Bits)
VENC_HTRIGGER_VTRIGGER RW 32 0x60 0x4805 0C60
VENC_SAVID_EAVID RW 32 0x64 0x4805 0C64
VENC_FLEN_FAL RW 32 0x68 0x4805 0C68
VENC_LAL_PHASE_RESET RW 32 0x6C 0x4805 0C6C
VENC_HS_INT_START_STOP_X RW 32 0x70 0x4805 0C70
VENC_HS_EXT_START_STOP_X RW 32 0x74 0x4805 0C74
VENC_VS_INT_START_X RW 32 0x78 0x4805 0C78
VENC_VS_INT_STOP_X_VS_INT_START_Y RW 32 0x7C 0x4805 0C7C
VENC_VS_INT_STOP_Y_VS_EXT_START_X RW 32 0x80 0x4805 0C80
VENC_VS_EXT_STOP_X_VS_EXT_START_Y RW 32 0x84 0x4805 0C84
VENC_VS_EXT_STOP_Y RW 32 0x88 0x4805 0C88
VENC_AVID_START_STOP_X RW 32 0x90 0x4805 0C90
VENC_AVID_START_STOP_Y RW 32 0x94 0x4805 0C94
VENC_FID_INT_START_X_FID_INT_START_Y RW 32 0xA0 0x4805 0CA0
VENC_FID_INT_OFFSET_Y_FID_EXT_START_ RW 32 0xA4 0x4805 0CA4
X
VENC_FID_EXT_START_Y_FID_EXT_OFFSET RW 32 0xA8 0x4805 0CA8
_Y
VENC_TVDETGP_INT_START_STOP_X RW 32 0xB0 0x4805 0CB0
VENC_TVDETGP_INT_START_STOP_Y RW 32 0xB4 0x4805 0CB4
VENC_GEN_CTRL RW 32 0xB8 0x4805 0CB8
VENC_OUTPUT_CONTROL RW 32 0xC4 0x4805 0CC4
VENC_OUTPUT_TEST RW 32 0xC8 0x4805 0CC8
7.7.1.7 DSI Protocol Engine Register Mapping Summary
Table 7-123. DSI Protocol Engine Register Mapping Summary
Register Name Type Register Width (Bits) Address Offset Physical Address
DSI_REVISION R 32 0x000 0x4804 FC00
DSI_SYSCONFIG RW 32 0x010 0x4804 FC10
DSI_SYSSTATUS R 32 0x014 0x4804 FC14
DSI_IRQSTATUS RW 32 0x018 0x4804 FC18
DSI_IRQENABLE RW 32 0x01C 0x4804 FC1C
DSI_CTRL RW 32 0x040 0x4804 FC40
DSI_COMPLEXIO_CFG RW 32 0x048 0x4804 FC48
1
DSI_COMPLEXIO_IRQ RW 32 0x04C 0x4804 FC4C
STATUS
DSI_COMPLEXIO_IRQ RW 32 0x050 0x4804 FC50
ENABLE
DSI_CLK_CTRL RW 32 0x054 0x4804 FC54
DSI_TIMING1 RW 32 0x058 0x4804 FC58
DSI_TIMING2 RW 32 0x05C 0x4804 FC5C
DSI_VM_TIMING1 RW 32 0x060 0x4804 FC60
DSI_VM_TIMING2 RW 32 0x064 0x4804 FC64
DSI_VM_TIMING3 RW 32 0x068 0x4804 FC68
DSI_CLK_TIMING RW 32 0x06C 0x4804 FC6C
DSI_TX_FIFO_VC_SIZE RW 32 0x070 0x4804 FC70
1816Display Subsystem SWPU177N – December 2009 – Revised November 2010
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