Public Version
Display Subsystem Register Manual
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Table 7-340. VENC_VS_INT_STOP_X_VS_INT_START_Y
Address Offset
0x7C
Physical address
0x4805 0C7C
Instance
VENC
Description
VENC VS_INT_STOP_X and VS_INT_START_Y
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
VS_INT_START_Y
Reserved
VS_INT_STOP_X
Bits
Field Name
Description
Type
Reset
31:26
Reserved
Reserved. Read returns 0s.
RW
0x00
25:16
VS_INT_START_Y
VSYNC internal start. These bits define VSYNC INTERNAL start line
RW
0x209
value
15:10
Reserved
Reserved. Read returns 0s.
RW
0x00
9:0
VS_INT_STOP_X
VSYNC internal stop. These bits define VSYNC internal stop pixel
RW
0x1A0
value
Table 7-341. Register Call Summary for Register VENC_VS_INT_STOP_X_VS_INT_START_Y
Display Subsystem Basic Programming Model
•
Video Encoder Register Settings
Display Subsystem Register Manual
•
Video Encoder Register Mapping Summary
:
Table 7-342. VENC_VS_INT_STOP_Y_VS_EXT_START_X
Address Offset
0x80
Physical address
0x4805 0C80
Instance
VENC
Description
VENC VS_INT_STOP_Y and VS_EXT_START_X
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
VS_EXT_START_X
Reserved
VS_INT_STOP_Y
Bits
Field Name
Description
Type
Reset
31:26
Reserved
Reserved. Read returns 0s.
RW
0x00
25:16
VS_EXT_START_X
VSYNC external start. These bits define VSYNC external start pixel
RW
0x1AC
value.
15:10
Reserved
Reserved. Read returns 0s.
RW
0x00
9:0
VS_INT_STOP_Y
VSYNC internal stop. These bits define VSYNC INTERNAL stop line
RW
0x022
value.
Table 7-343. Register Call Summary for Register VENC_VS_INT_STOP_Y_VS_EXT_START_X
Display Subsystem Basic Programming Model
•
Video Encoder Register Settings
Display Subsystem Register Manual
•
Video Encoder Register Mapping Summary
:
1900
Display Subsystem
SWPU177N – December 2009 – Revised November 2010
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