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Display Subsystem Register Manual
Table 7-121. RFBI Register Mapping Summary (continued)
Register Name
Type
Register Width
Address Offset
Physical Address
(Bits)
R
32
0x14
0x4805 0814
RW
32
0x40
0x4805 0840
RW
32
0x44
0x4805 0844
RW
32
0x48
0x4805 0848
W
32
0x4C
0x4805 084C
W
32
0x50
0x4805 0850
W
32
0x54
0x4805 0854
RW
32
0x58
0x4805 0858
RW
32
0x5C
0x4805 085C
RW
32
0x60+ (i* 0x18)
(1)
0x4805 0860+ (i* 0x18)
(1)
RW
32
0x64+ (i* 0x18)
(1)
0x4805 0864+ (i* 0x18)
(1)
RW
32
0x68+ (i* 0x18)
(1)
0x4805 0868+ (i* 0x18)
(1)
RW
32
0x6C+ (i* 0x18)
(2)
0x4805 086C+ (i* 0x18)
(2)
RW
32
0x70+ (i* 0x18)
(2)
0x4805 0870+ (i* 0x18)
(2)
RW
32
0x74+ (i* 0x18)
(2)
0x4805 0874+ (i* 0x18)
(2)
RW
32
0x90
0x4805 0890
RW
32
0x94
0x4805 0894
(1)
i = 0 to 1
(2)
i = 0 to 1
7.7.1.6
Video Encoder Register Mapping Summary
Table 7-122. Video Encoder Register Mapping Summary
Register Name
Type
Register Width
Address Offset
Physical Address
(Bits)
R
32
0x00
0x4805 0C00
R
32
0x04
0x4805 0C04
RW
32
0x08
0x4805 0C08
RW
32
0x10
0x4805 0C10
RW
32
0x14
0x4805 0C14
RW
32
0x1C
0x4805 0C1C
RW
32
0x20
0x4805 0C20
RW
32
0x24
0x4805 0C24
RW
32
0x28
0x4805 0C28
RW
32
0x2C
0x4805 0C2C
RW
32
0x30
0x4805 0C30
RW
32
0x34
0x4805 0C34
RW
32
0x38
0x4805 0C38
RW
32
0x3C
0x4805 0C3C
RW
32
0x40
0x4805 0C40
RW
32
0x44
0x4805 0C44
RW
32
0x48
0x4805 0C48
RW
32
0x4C
0x4805 0C4C
RW
32
0x50
0x4805 0C50
RW
32
0x54
0x4805 0C54
RW
32
0x58
0x4805 0C58
RW
32
0x5C
0x4805 0C5C
1815
SWPU177N – December 2009 – Revised November 2010
Display Subsystem
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