Texas Instruments OMAP36 Series, Technical Reference Manual

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Display Subsystem Register Manual
Table 7-297. Register Call Summary for Register VENC_HFLTR_CTRL
Display Subsystem Basic Programming Model
• Video Encoder Register Settings : [0]
Display Subsystem Register Manual
• Video Encoder Register Mapping Summary : [1]
• Video Encoder Registers : [2]
Table 7-298. VENC_CC_CARR_WSS_CARR
Address Offset 0x28
Physical address 0x4805 0C28 Instance VENC
Description Frequency code control
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FWSS FCC
Bits Field Name Description Type Reset
31:16 FWSS Wide screen signaling run-in code frequency control RW 0x043F
For common values for FWSS[15:0] bit field, refer to Table 7-44
Reset value is for NTSC-601standard
15:0 FCC Close caption run-in code frequency control RW 0x2631
For common values for FCC[15:0] bit field refer to Table 7-42 . Reset value is
for NTSC-601 standard
Table 7-299. Register Call Summary for Register VENC_CC_CARR_WSS_CARR
Display Subsystem Functional Description
• Closed Caption Encoding : [0] [1] [2]
• Wide-Screen Signaling (WSS) Encoding : [3] [4]
Display Subsystem Basic Programming Model
• Video Encoder Register Settings : [5]
Display Subsystem Register Manual
• Video Encoder Register Mapping Summary : [6]
Table 7-300. VENC_C_PHASE
Address Offset 0x2C
Physical address 0x4805 0C2C Instance VENC
Description VENC_C_PHASE
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved CPHS
Bits Field Name Description Type Reset
31:8 Reserved Reserved. Read returns 0. RW 0x000000
7:0 CPHS Phase of the encoded video color subcarrier (including the color burst) RW 0x00
relative to H-sync. The adjustable step is 360/256 degrees.
1887 SWPU177N – December 2009 – Revised November 2010 Display Subsystem
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