Texas Instruments OMAP36 Series, Technical Reference Manual

Page: 1694 / 3738

B E
S
T
A
R
T
P
A
R
I
T
Y
P
A
R
I
T
Y
0.503/0.5 MHz
50 IRE
40 IRE
Byte2
D0-D6
Byte1
D0-D6
Hsync
Color Burst
Clock Run-in
Start Bit
Null character 2
Null character 1
0
dss-080
Public Version
Display Subsystem Functional Description
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The running clock frequency is controlled by the DSS. VENC_CC_CARR_WSS_CARR [15:0] FCC bit field
which should be kept at reset value (0x2631) to get 5034960.5Hz (32xfline) for NTSC-601. The
closed-caption running clock common frequencies are detailed in
Table 7-42 .
Table 7-42. Closed-Caption Run Clock Frequency Settings
NTSC Square
NTSC-601 PAL-601 PAL Square Pixel
Pixel
VENC_CC_CARR_WSS_C
ARR [15:0] FCC bit field 0x2631 0x25ED 0x2A03 0x22B6
value
The closed-caption data is encoded in nonreturn-to-zero (NRZ) format. Additionally, the data translates to
the IRE scale as follows: 0 = 0 IRE; 1 = 50 IRE.
Figure 7-107 shows the parameters of closed-caption line data implemented in different standards.
Figure 7-107. Closed Captioning Timing
NOTE:
• The interval A is controlled by the DSS. VENC_LN_SEL [25:16] LN21_RUNIN bit field.
• The interval B is controlled by DSS. VENC_CC_CARR_WSS_CARR [15:0] FCC bit field.
Table 7-43. Closed-Caption Standard Timing Values
Intervals Description Timing Values for Encoding Timing Values for Decoding
Minimal Nominal Maximal Lower Bound Nominal Upper Bound
A HSYNC to clock running 10.250 µs 10.500 µs 10.750 µs 10.000 µs 10.500 µs 11.000 µs
B Clock running 12.910 µs 12.910 µs
Clock running to third start
C 3.972 µs 3.972 µs
bit
D Start bit 1.986 µs 1.986 µs
E Data characters 31.778 µs 31.778 µs
NOTE: All timing values listed in Table 7-43 are measured from the mid-point (half amplitude) on all
edges.
For a complete description of copy protection including CGMS-A, please refer to CEA-608-x standard
1694 Display Subsystem SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated