Texas Instruments OMAP36 Series, Technical Reference Manual

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Display Subsystem Register Manual
Table 7-252. RFBI_PIXEL_CNT
Address Offset 0x44
Physical address 0x4805 0844 Instance RFBI
Description The control register configures the RFBI pixel count value.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PIXELCNT
Bits Field Name Description Type Reset
31:0 PIXELCNT Pixel counter value RW 0x00000000
The S/W indicates the number of pixels to transfer to the LCD panel
frame buffer. The value is set when the module is disabled. During
the transfer the HW decrements the register when a pixel has been
sent to the RFB.
Table 7-253. Register Call Summary for Register RFBI_PIXEL_CNT
Display Subsystem Basic Programming Model
• RFBI Control Registers : [0]
• Enable : [1]
• Number of Pixels to Transfer : [2] [3] [4]
Display Subsystem Register Manual
• RFBI Register Mapping Summary : [5]
Table 7-254. RFBI_LINE_NUMBER
Address Offset 0x48
Physical address 0x4805 0848 Instance RFBI
Description The control register configures the number of lines to synchronize the beginning of the transfer.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved LINENUMBER
Bits Field Name Description Type Reset
31:11 Reserved Write 0s for future compatibility RW 0x000000
Read returns 0
10:0 LINENUMBER Programmable line number RW 0x000
Line number from 0 to 2
11
-1. Number of HSYNC after the VSYNC
occurs before the beginning of the transfer.
Table 7-255. Register Call Summary for Register RFBI_LINE_NUMBER
Display Subsystem Basic Programming Model
• RFBI Control Registers : [0]
Display Subsystem Register Manual
• RFBI Register Mapping Summary : [1]
1871 SWPU177N – December 2009 – Revised November 2010 Display Subsystem
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