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Display Subsystem Basic Programming Model
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•
ERRCONTENTIONLP0_i_IRQ: ERRCONTENTION0LPDX
and ERRCONTENTION0LPDY are asserted when the Lane module detects a contention situation
on lines DX and DY respectively while trying to drive the lines low. Contention is detected only if it
lasts at least 50ns
•
ERRCONTENTIONLP1_i_IRQ: ERRCONTENTION1LPDX
and ERRCONTENTION1LPDY are asserted when the Lane module detects a contention situation
on lines DX and DY respectively while trying to drive the lines high. Contention is detected only if it
lasts at least 50ns
The ULPSACTIVENOT signal goes low which indicates to the protocol that the PHY has entered ULP
state. When all the ULPSActiveNot signals are low, the DSS.
ULPSACTIVENOT_ALL0_IRQ event is generated. When all the ULPSActiveNot signals are high, the
DSS.
[31] ULPSACTIVENOT_ALL1_IRQ event is generated.
When any of the events defined in DSS.
register happened, the
DSS.
[10] COMPLEXIO_ERR_IRQ bit is set to 1 at DSI protocol engine level.
The software must take appropriate action when receiving the interrupt indicating the error from the
complex I/O. The action can be:
•
Reset of the DSI protocol engine module
•
Reset of the peripheral though reset trigger or directly driving the hardware reset pin of the display
module
•
Ignore the error
7.5.7 RFBI Basic Programming Model
The RFBI programming model must be used for LCD display support only.
7.5.7.1
DISPC Control Registers
The following DISPC registers are used in RFBI mode:
•
The STALL mode is selected by setting the DSS.
[11] STALLMODE bit. The
DSS.
[5] GOLCD bit must not be set to 1, but the display controller configuration
(DMA engine, pipelines associated to the LCD output,..) must be set before enabling the LCD output
by setting the DSS.
[0] LCDENABLE bit to 1.
•
To enable the hardware handcheck to avoid underflow, the DSS.
[16]
FIFOHANDCHECK must be set to 1. The reset value of this bit is 0. The handcheck applies to the
pipelines connected to the LCD output. It must be disabled before resetting the
DSS.
[11] STALLMODE bit to 0. The new setting for the FIFO handcheck is used for
the following frames.
NOTE:
The LCD output is disabled at the end of the transfer of the frame. The software must
reenable the LCD output to generate a new frame by setting the DSS.
[0]
LCDENABLE to 1. See
.
7.5.7.2
RFBI Control Registers
The following registers define the RFBI control registers:
•
DSS.
•
DSS.
•
DSS.
7.5.7.2.1 High Threshold
The DSS.
[6:5] HIGHTHRESHOLD bit field is used to define the threshold to be used for
the generation of the DMA request to receive data into the interconnect FIFO (24 x 32 FIFO depth)
through the address of the register
. It must be the size of the burst. The supported values are
1764
Display Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
