Public Version
Display Subsystem Register Manual
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Table 7-382. DSI_COMPLEXIO_IRQSTATUS
Address Offset
0x0000 004C
Physical Address
0x4804 FC4C
Instance
DSI_PROTOCOL_ENGINE
Description
INTERRUPT STATUS REGISTER - All errors from complex I/O
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
ERRESC3_IRQ
ERRESC2_IRQ
ERRESC1_IRQ
STATEULPS3_IRQ
STATEULPS2_IRQ
STATEULPS1_IRQ
ERRSYNCESC3_IRQ
ERRSYNCESC2_IRQ
ERRSYNCESC1_IRQ
ERRCONTROL3_IRQ
ERRCONTROL2_IRQ
ERRCONTROL1_IRQ
ULPSACTIVENOT_ALL1_IRQ
ULPSACTIVENOT_ALL0_IRQ
ERRCONTENTIONLP1_3_IRQ
ERRCONTENTIONLP0_3_IRQ
ERRCONTENTIONLP1_2_IRQ
ERRCONTENTIONLP0_2_IRQ
ERRCONTENTIONLP1_1_IRQ
ERRCONTENTIONLP0_1_IRQ
Bits
Field Name
Description
Type
Reset
31
ULPSACTIVENOT_
All the ULPSActiveNOT signals corresponding to the lanes with
RW
0x0
ALL1_IRQ
TXULPSExit being high are high.
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
30
ULPSACTIVENOT_
All signals ULPSActiveNOT are 0
RW
0x0
ALL0_IRQ
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
29
RESERVED
Write 0s for future compatibility.
RW
0x0
Reads returns 0.
28
RESERVED
Write 0s for future compatibility.
RW
0x0
Reads returns 0.
27
RESERVED
Write 0s for future compatibility.
RW
0x0
Reads returns 0.
26
RESERVED
Write 0s for future compatibility.
RW
0x0
Reads returns 0.
25
ERRCONTENTIONLP1_
Contention LP1 error for lane #3
RW
0x0
3_IRQ
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
24
ERRCONTENTIONLP0_
Contention LP0 error for lane #3
RW
0x0
3_IRQ
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
23
ERRCONTENTIONLP1_
Contention LP1 error for lane #2
RW
0x0
2_IRQ
0x0: READS: Event is false.
WRITES: Status bit unchanged.
0x1: READS: Event is true (pending).
WRITES: Status bit is reset.
1922
Display Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated