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Display Subsystem Basic Programming Model
4x32, 8x32 and 16x32. The system DMA receives the DMA request and is in charge of providing the
correct number of bytes. If the DSS.
[7] DISABLE_DMA_REQ bit is reset, the DMA
request is generated when there is enough room in the interconnect FIFO to accept the full burst. In case
the RFBI receives writes L4 requests to the
location when the interconnect FIFO is full, the
request is not accepted. The RFBI waits for a free entry in the interconnect FIFO to accept the L4 request.
If the DSS.
[7] DISABLE_DMA_REQ bit is set, the DMA request is not generated. The
threshold value is ignored.
NOTE:
Software users can access the
location without using the DMA request and
without programming the high threshold value (backward mode).
7.5.7.2.2 Bypass Mode
Setting the DSS.
[1] BYPASSMODE bit directly outputs the LCD controller output to the
LCD panel. Resetting this bit directs the MPU module to send commands/parameters and data from the
input video port FIFO.
7.5.7.2.3 Enable
Setting/resetting the DSS.
[0] ENABLE bit enables/disables the RFBI module. The
hardware resets the enable bit after all of the pixels are sent to the panel. The
DSS.
[31:0] PIXELCNT bit field value defines the number of pixels to send to the LCD
panel. When the transfer is finished, the configuration used can be modified.
Table 7-69. RFBI Behavior
[1] BYPASSMODE
[0] ENABLE bit value
RFBI Behavior
bit value
0
0
L4 interconnect can write
command/param/data and read
data/status from the Remote Frame
Buffer (RFB). L4 interconnect access can
only be done to the CSx actually active
0
1
The DISPC sends pixels to the RFB.
The stall signal is asserted when the module is disabled. Through the L4 port, pixels can be sent to the
LCD panel only when the pixel count has reach the value 0x0
NOTE:
The LCD output is disabled at the end of the transfer of the frame. The software must
reenable the LCD output to generate a new frame by setting the DSS.
[0]
LCDENABLE to 1. See
.
7.5.7.2.4 Configuration Selection
Setting the DSS.
[3:2] CONFIGSELECT bit field selects the configuration number (1 or 0
if bits are set or reset). The registers associated with the configuration output the data to the LCD panel.
If both chip-selects are selected, the configuration for the first chip-select is used (except for the polarity of
the RFBI_CS1 signal defined by the second configuration) and both devices connected to the CS signals
are driven in parallel. In read mode, if both chip-selects are set, only RFBI_CS0 is asserted to read data
from the device connected on RFBI_CS0. In write mode with two chip-selects selected, the RFBI can write
to the two devices simultaneously.
1765
SWPU177N – December 2009 – Revised November 2010
Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated
