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Display Subsystem Basic Programming Model
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7.5.7.2.5 ITE Bit
Set the DSS.
[4] ITE bit to start capturing the data from the display controller. This bit has
no effect if the trigger mode is set to external. The display controller must be configured in the STALL
mode to account for the RFBI_DISPC_STALL signal. Setting the trigger mode to external
(DSS.
[3:2] TRIGGERMODE bit field set to 0x1 or 0x2) causes the
[4] ITE bit to be ignored. The corresponding chip-select must be selected when this
bit is set by users.
The RFBI_DISPC_STALL signal is asserted when at least one of the following cases occur:
•
Default status when no data to capture from the display controller
•
High FIFO threshold reached
•
End of the transfer (number of data to output)
•
Reset of the RFBI module
•
DSS.
[0] ENABLE bit reset to 0x0
The RFBI_DISPC_STALL signal is deasserted when the DSS.
[0] ENABLE bit is set to
0x1 and at least one of the following cases occur:
•
Low FIFO threshold reached
•
External TE occurs and the DSS.
[3:2] TRIGGERMODE bit field is set to 0x1 or 0x2 for
automatic external trigger (start of the transfer, the FIFO pointers are reset, the FIFO is empty).
•
DSS.
[4] ITE bit set to 0x1 by users (start of the transfer, the FIFO pointers are reset,
the FIFO is empty).
7.5.7.2.6 Number of Pixels to Transfer
Setting the DSS.
[31:0] PIXELCNT bit field value directs the application to indicate the
number of pixels to be transferred to the LCD panel. The value can be changed only when the
DSS.
[0] ENABLE is reset.
During the transfer, the hardware decrements the register when a pixel is sent to the remote frame buffer.
When the DSS.
[0] ENABLE bit is set and a new value is written in the
register when the current value in the register is a non-zero (the remaining
number of pixels to transfer), the ongoing transfer is aborted.
From the L4 interconnect side, if the DSS.
[10:9] CYCLEFORMAT bit field is equal to 0x3
and the DSS.
[8:7] L4FORMAT bit field is equal to 0x0, an even number of write accesses
to the data register must be performed before accessing any other register
(CMD/PARAM/STATUS/READ).
When the DSS.
[10:9] CYCLEFORMAT bit field is 0x3 (2 pixels are sent over 3 cycles), the
number of pixels to be programmed in the DSS.
[31:0] PIXELCNT bit field must be a
multiple of 2. If another CYCLEFORMAT is used, the value for PIXELCNT can be odd or even. This
constraint is valid for data provided on the L4 interconnect port and from the display controller.
If the DSS.
[10:9] CYCLEFORMAT bit field is equal to 0x3, the DSS.
[8:7]
L4FORMAT bit field is equal to 0, and back-to-back register write is processed. The following registers
should be written after the first data:
, and
. The
whole data transfer must first be performed before being able to write to any other registers (
, and
).
7.5.7.2.7 Programmable Line Number
When the trigger mode is set to external trigger mode with HSYNC and VSYNC or the TE, hardware
resets the line counter when the VSYNC occurs and, after a programmable number of lines (the HSYNC
pulse occurs for every line), the transfer to the LCD panel begins. When the programmable line number is
0, only the VSYNC pulse indicates the beginning of the transfer in both modes: HSYNC/VSYNC and TE
(logical OR operation between HSYNC and VSYNC).
7.5.7.3
RFBI Configuration
The following registers define the RFBI configuration:
1766
Display Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
