Public Version
Display Subsystem Register Manual
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Bits
Field Name
Description
Type
Reset
31:19
Reserved
Reserved. Read returns 0s.
RW
0x0000
18:17
PRES
Phase reset mode.
RW
0x3
0x0:
No reset
0x1:
Reset every two lines
0x2:
Reset every eight fields. Color subcarrier phase is reset to
VENC_CPHASE[7:0] CPHS field value (offset 0x2C) upon reset
0x3:
Reset every four fields. Color subcarrier phase is reset to
VENC_CPHASE[7:0] CPHS bit field value (offset 0x2C) upon
reset
16
SBLANK
Data output enable
RW
0
0x0:
No functionality
0x1:
Enables the output of data when
[10]
VBLMK bit is '0b1'.
15:9
Reserved
Reserved. Read returns 0s.
RW
0x00
8:0
LAL
Last Active Line of Field. These bits define the last active line of a field. The
RW
0x107
LAL[8:0] bit field value must be set to a value lower than the active window.
Table 7-333. Register Call Summary for Register VENC_LAL_PHASE_RESET
Display Subsystem Basic Programming Model
•
Video Encoder Register Settings
Display Subsystem Register Manual
•
Video Encoder Register Mapping Summary
:
•
Table 7-334. VENC_HS_INT_START_STOP_X
Address Offset
0x70
Physical address
0x4805 0C70
Instance
VENC
Description
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
HS_INT_STOP_X
Reserved
HS_INT_START_X
Bits
Field Name
Description
Type
Reset
31:26
Reserved
Reserved. Read returns 0s.
RW
0x00
25:16
HS_INT_STOP_X
HSYNC internal stop. These bits define HSYNC internal stop pixel
RW
0x07E
value
15:10
Reserved
Reserved. Read returns 0s.
RW
0x00
9:0
HS_INT_START_X
HSYNC internal start. These bits define HSYNCI NTERNAL start
RW
0x34E
pixel value
Table 7-335. Register Call Summary for Register VENC_HS_INT_START_STOP_X
Display Subsystem Basic Programming Model
•
Video Encoder Register Settings
Display Subsystem Register Manual
•
Video Encoder Register Mapping Summary
:
•
1898
Display Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated