Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 1919 / 3738

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Display Subsystem Register Manual
Table 7-379. Register Call Summary for Register DSI_CTRL (continued)
Display Subsystem Functional Description
• Clock Requirements : [13]
• Command Mode : [14] [15] [16] [17]
• DSI-PLL Power FSM : [18] [19] [20] [21]
• TurnRequest FSM : [22] [23]
• HS TX Timer : [24] [25]
• LP RX Timer : [26] [27]
• Bus Turnaround : [28] [29] [30] [31]
• Reset : [32] [33] [34]
• Tearing Effect : [35]
• ECC Generation : [36]
• Checksum Generation for Long Packet Payloads : [37]
• End of Transfer Packet : [38]
Display Subsystem Basic Programming Model
• Global Register Controls : [39] [40] [41] [42] [43] [44] [45]
• Packets : [46] [47] [48] [49] [50] [51]
• Video Mode : [52] [53] [54] [55]
• Video Port Data Bus : [56]
• Command Mode TX FIFO : [57] [58]
• Video Mode Transfer : [59]
• Command Mode Transfer Example 1 : [60]
• Command Mode Transfer Example 2 : [61]
Display Subsystem Use Cases and Tips
• Set Up DSI Control Registers : [62] [63] [64] [65] [66] [67] [68] [69] [70] [71] [72] [73] [74] [75]
• Enable Video Mode Using the DISPC Video Port : [76] [77]
• Configure DSI Protocol Engine : [78] [79] [80] [81] [82] [83] [84] [85] [86]
• Enable Command Mode Using DISPC Video Port : [87] [88] [89] [90]
Display Subsystem Register Manual
• DSI Protocol Engine Register Mapping Summary : [91]
• DSI Protocol Engine Registers : [92] [93] [94] [95] [96] [97] [98] [99]
Table 7-380. DSI_COMPLEXIO_CFG1
Address Offset 0x0000 0048
Physical Address 0x4804 FC48 Instance DSI_PROTOCOL_ENGINE
Description COMPLEXIO CONFIGURATION REGISTER for the complex I/O This register contains the lane
configuration for the order and position of the lanes (clock and data) and the polarity order for the control
of the PHY differential signals in addition to the control bit for the power FSM.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GOBIT
PWR_CMD
RESERVED RESERVED RESERVED RESERVED RESERVED
DATA2_POL DATA1_POL
CLOCK_POL
SHADOWING
RESET_DONE PWR_STATUS
DATA2_POSITION DATA1_POSITION
CLOCK_POSITION
USE_LDO_EXTERNAL
LDO_POWER_GOOD_STATE
1919 SWPU177N – December 2009 – Revised November 2010 Display Subsystem
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