Texas Instruments OMAP36 Series, Technical Reference Manual

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Display Subsystem Use Cases and Tips
Table 7-88. DSI Control Registers (continued)
Steps Registers Value
Set the arbitration scheme for granting the VC pending ready
DSI_CTRL [3] TX_FIFO_ARBITRATION 0x1
requests in the TX FIFO as Sequential Scheme.
Enable the ECC check for the received header. DSI_CTRL [2] ECC_RX_EN 0x1
Table 7-89. DSI Complex I/O Registers
Steps Registers Value
GOBIT, complex I/O power ON, select data, and clock position DSI_COMPLEXIO_CFG1 0x4800 0032
Clear Reg DSI_COMPLEXIO_IRQSTATUS 0xC3F39CE7
Disable IRQ DSI_COMPLEXIO_IRQENABLE 0x0
Enable I/F DSI_CTRL [0] IF_EN 0x1
Disable I/F DSI_CTRL [0] IF_EN 0x0
Wait until IF_EN = 0 DSI_CTRL [0] IF_EN Read 0x0
Enable Low Power clock DSI_CLK_CTRL [20] LP_CLK_ENABLE 0x1
Reset is done. DSI_COMPLEXIO_CFG1 [29] RESET_DONE Read 0x1
Power control is on. DSI_COMPLEXIO_CFG1 [26:25] PWR_STATUS Read 0x1
Reset is complete. DSI_SYSSTATUS [0] RESETDONE Read 0x1
7.6.4.2.4.2 Configure DSI Timing and Virtual Channels
Table 7-90 lists the steps to configure DSI timing and the virtual channels.
Table 7-90. DSI Timing Registers
Steps Registers Value
STOP_STATE_COUNTER_IO = 0x999 DSI_TIMING1 [31:0] 0x0000 0999
HS_TX_TO_X8, HS_TX_TO_COUNTER = 0x0FD2,
DSI_TIMING2 [31:0] 0x2FD2 40CD
LP_RX_TO_X16, LP_RX_TO_COUNTER = 0x00CD
(HSA<<24)|(HFP<<12)|HBP DSI_VM_TIMING1 [31:0] 0x0000 700A
(WINDOW_SYNC<<24)|(VSA<<16)|(DSI_VFP<<8)|VBP DSI_VM_TIMING2 [31:0] 0x0401 0101
(TL<<16)|DSI_VACT DSI_VM_TIMING3 [31:0] 0x05BB 0280
(ENTER_HS_MODE_LATENCY<<16)|EXIT_HS_MODE_LATEN 0x0000
DSI_VM_TIMING7 [31:0]
CY C000A
DDR_CLK_PRE<<8|DDR_CLK_POST DSI_CLK_TIMING [31:0] 0x0000 0F0B
HS speed, ECC generation for the Transmit, Enable CheckSum
DSI_VC0_CTRL[31:0] 0x2080 0390
generation for the Payload.
• Freq TxByteClkHS:
FHSB = FCLKIN4DDR/16
FVPP = FCLKIN4DDR/((RegM3 + 1) × DISPC_LCD * DISPC_PCD)
FVP = FCLKIN4DDR/(RegM3 + 1) (28)
1799 SWPU177N – December 2009 – Revised November 2010 Display Subsystem
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