Texas Instruments OMAP36 Series, Technical Reference Manual

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Display Subsystem Register Manual
Bits Field Name Description Type Reset
13 RESERVED Write 0s for future compatibility. RW 0x0
Reads returns 0.
12:11 RESERVED Write 0s for future compatibility. RW 0x0
Reads returns 0.
10 RESERVED Write 0s for future compatibility. RW 0x0
Reads returns 0.
9 PLL_RECAL_IRQ_EN PLL recalibration event (assertion of recalibration signal from RW 0x0
the DSI PLL Control module)
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
8 PLL_UNLOCK_IRQ_EN PLL un-lock event (de-assertion of lock signal from the DSI RW 0x0
PLL Control module)
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
7 PLL_LOCK_IRQ_EN PLL lock event (assertion of lock signal from the DSI PLL RW 0x0
Control module)
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
6 RESERVED Write 0s for future compatibility. RW 0x0
Reads returns 0.
5 RESYNCHRONIZATION_ Resynchronization RW 0x0
IRQ_EN
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
4 WAKEUP_IRQ_EN Wakeup RW 0x0
0x0: Event is masked
0x1: Event generates an interrupt when it occurs
3:0 RESERVED Write 0s for future compatibility. RW 0x0
Reads returns 0.
Table 7-377. Register Call Summary for Register DSI_IRQENABLE
Display Subsystem Functional Description
• Tearing Effect : [0]
• Acknowledge : [1]
Display Subsystem Basic Programming Model
• Interrupts : [2]
Display Subsystem Use Cases and Tips
• Set Up DSI Control Registers : [3]
• Configure DSI Protocol Engine : [4]
Display Subsystem Register Manual
• DSI Protocol Engine Register Mapping Summary : [5]
Table 7-378. DSI_CTRL
Address Offset 0x0000 0040
Physical Address 0x4804 FC40 Instance DSI_PROTOCOL_ENGINE
Description GLOBAL CONTROL REGISTER This register controls the DSI Protocol Engine module. This register
should not be modified dynamically (except IF_EN bit field).
Type RW
1915 SWPU177N – December 2009 – Revised November 2010 Display Subsystem
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