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Display Subsystem Functional Description
7.4.3.9
PHY Triggers
The DSI protocol engine uses three triggers, which are supported only for data lane 1:
•
Reset from host to display
•
Tearing effect (TE) from display to host
•
Acknowledge from display to host
CAUTION
Each trigger is associated with a dedicated user-configurable receive or
transmit pattern, loaded in
or
bit fields. The default (reset) values of the bit fields are aligned with the MIPI
D-PHY specification v0.92. If the user needs to change any of these values, the
following must be considered:
•
If any of the bit fields are written with a nondefault value, the other bit fields
in the same register must also be configured with different values. This is to
ensure that two different trigger bit fields are not programmed with the same
pattern.
•
If two or more bit fields are written with equal values, this may lead to
unpredictable behavior of the DSI PHY module.
7.4.3.9.1 Reset
The DSI protocol engine can use one of the triggers of the DSI_PHY to send a reset to the display. The
reset trigger pattern is configurable through the
[31:24] REG_TXTRIGGERESC3
bit field. To send the reset pattern to the peripheral, the DSS.
[5] TRIGGER_RESET bit must be
set to 1. When the software requires the trigger reset pattern to be sent, the DSI protocol engine resets its
own logic but not the registers. The software can select between two reset modes:
•
Immediate reset: All pending requests in TX FIFO not already taken into account for transfer
scheduling, the RX FIFO requests, and the data from video port are ignored. Only the current transfer
on DSI link and already scheduled ones are transmitted. All the other transfers are discarded.
•
Synchronized reset: The mode is only valid if there is VC using the video mode and if it is active. The
principle is to wait for the current video frame to be transferred on the link. Any data on VP after the
current frame are ignored.
To select the reset mode, software users must program the DSS.
TRIGGER_RESET_MODE.
CAUTION
For both reset modes, the hardware should flush the FIFOs, synchronization
buffers, and line buffers before resetting the DSS.
[0] IF_EN bit.
7.4.3.9.2 Tearing Effect
The TE on the display is avoided by having synchronization information from the display. It is used only in
command mode. In case of video mode, it is not functional. Users are responsible for selecting the
command mode for the VC using the TE feature.
The software must set and send the appropriate sequence to receive the TE trigger pattern from the
peripheral. The value of the expected TE trigger pattern can be configured through the
[23:16] REG_RXTRIGGERESC2 bit field. When the TE trigger pattern is received,
the DSI protocol engine generates the TE_TRIGGER_IRQ interrupt with TE event if the interrupt is
enabled. To enable the interrupt, set to 1 the DSS.
[16] TE_TRIGGER_IRQ_EN bit. The
[16] TE_TRIGGER_IRQ status bit indicates if the interrupt event has been
generated.
1681
SWPU177N – December 2009 – Revised November 2010
Display Subsystem
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