Texas Instruments OMAP36 Series, Technical Reference Manual

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dss-E127
= ´ ´ ´ -
=
Re gM3 ((BPP 2) /(DISPC _ LCD DISPC _ PCD NDL)) 1
Re gM3 15
dss-E128
= ´
= -
=
=
=
FCLKIN4DDR FCLKIN 4
Re gN (FDSI _ PLL _ REFCLK / F INt) 1
FDSI _ PLL _ REFCLK 26 MHz (system clock)
Fint 2 MHz (reduce PLL lock time)
Re gN 12
dss-E129
= + ´ ´
= ´
=
Re gM ((Re gN 1) (FCLKIN4DDR /(2 FDSI _ PLL _ REFCLK)))
FCLKIN4DDR 4 150 MHz
Re gM 150
Public Version
Display Subsystem Use Cases and Tips
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1. Calculate the divider value for the DSI protocol engine clock source:
RegM4 = FCLKIN4DDR/DSI2_PLL_FCLK – 1
FCLKIN4DDR = 4 x FCLKIN
RegM4 = 5
2. Determine LCD, PCD, and REGM3:
Calculate the divider value for DSS clock source: Same as Step 3.
3. Calculate N Divider for PLL:
4. Calculate M divider for PLL:
7.6.4.2.3 Switch to DSI PLL Clock Source
Select the DSI_PLL1 clock as the DISPC functional clock, and select the DSI_PLL2 clock as the DSI
functional clock: Set
DSS_CONTROL to 0x3.
7.6.4.2.4 Set Up DSI Protocol Engine
7.6.4.2.4.1 Set Up DSI Control Registers
Table 7-88 lists the steps to set up the DSI control registers. Table 7-89 lists the steps to set up the DSI
complex I/O registers.
Table 7-88. DSI Control Registers
Steps Registers Value
Enable SYNCLOST event. DSI_IRQENABLE [31:0] 0x4 0000
Set PACKET_SENT_IRQ_EN. DSI_VC0_IRQENABLE[31:0] 0x4
While the HSYNC START pulse is detected, the associated short
DSI_CTRL [17] VP_HSYNC_START 0x1
packet HSYNC START is generated.
While the VSYNC START pulse is detected, the associated short
DSI_CTRL [15] VP_VSYNC_START 0x1
packet VSYNC START is generated.
Set the trigger reset mode to immediate. DSI_CTRL [14] TRIGGER_RESET_MODE 0x1
Activate two line buffers. DSI_CTRL [13:12] LINE_BUFFER 0x2
HSYNC signal on the video port is active high. DSI_CTRL [10] VP_HSYNC_POL 0x1
VSYNC on the video port is active high. DSI_CTRL [11] VP_VSYNC_POL 0x1
Set the Data Enable signal on the video port as active high. DSI_CTRL [9] VP_DE_POL 0x1
Set the size of the video port data bus for the RGB format: 0x2
DSI_CTRL [7:6] VP_DATA_BUS_WIDTH 0x2
for RGB 888.
VP_CLK_RATIO is not used if video port is used to provide data
DSI_CTRL [4] VP_CLK_RATIO 0x0
in video mode
1798Display Subsystem SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated