Public Version
Display Subsystem Register Manual
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Bits
Field Name
Description
Type
Reset
31:2
RESERVED
Reads returns 0.
R
0x00000000
1
DSI_IRQ
DSI interrupt status (related to
R
0x0
0x0: DSI interrupt inactive
0x1: DSI interrupt active
0
DISPC_IRQ
DISPC interrupt status (related to
R
0x0
0x0: DISPC interrupt inactive
0x1: DISPC interrupt active
Table 7-133. Register Call Summary for Register DSS_IRQSTATUS
Display Subsystem Register Manual
•
Display Subsystem Register Mapping Summary
Table 7-134. DSS_CONTROL
Address Offset
0x040
Physical address
0x4805 0040
Instance
DISS
Description
This register contains the display subsystem control bits.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
DAC_DEMEN
VENC_OUT_SEL
DSI_CLK_SWITCH
DISPC_CLK_SWITCH
VENC_CLOCK_MODE
DAC_POWERDN_BGZ
VENC_CLOCK_4X_
ENABLE
Bits
Field Name
Description
Type
Reset
31:7
Reserved
Reserved for future DAC use
RW
0x0000000
6
VENC_OUT_SEL
Video DAC1 input selection:
RW
0
0x0: CVBS VENC output selected for composite video
mode
0x1: Luminance VENC output selected for s-video mode
5
DAC_POWERDN_BGZ
DAC Power-Down Control
RW
0
0x0: DAC Power-Down Band Gap powered down
0x1: DAC Power-Down Band Gap powered up
4
DAC_DEMEN
DAC dynamic element matching enable
RW
0
0x0: DAC Dynamic Element Matching Disabled
0x1: DAC Dynamic Element Matching Enabled
3
VENC_CLOCK_4X_
VENC clock 4x enable
RW
0
ENABLE
0x0: Disable
0x1: Enable
2
VENC_CLOCK_MODE
VENC clock mode. See
, Possible Digital
RW
0
Clock Division for the Video Encoder.
0x0: Mode 0. All three balanced clocks, derived from the
DSS_TV_CLK clock, are provided to the VENC, if the
VENC_CLOCK_4X_ENABLE bit [3] is set to 1 by
software.
0x1: Mode 1. The VENC_CLOCK_4X_ENABLE bit [3] is
used to control clock gating.
1820
Display Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated