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Display Subsystem Integration
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Video encoder functional clock
The DSS_TV_FCLK is divided into three balanced clocks, depending on the clock mode selected (see
Table 7-20. Possible Digital Clock Division for the Video Encoder
Clock Output
Clock Mode
Clock Mode 0
Clock Mode 1
Video encoder clock 4x
DSS_TV_FCLK
DSS_TV_FCLK or 0 (gated)
Video encoder clock 2x
DSS_TV_FCLK/2
DSS_TV_FCLK
Video encoder clock 1x
DSS_TV_FCLK/4
DSS_TV_FCLK/2
The clock mode is defined by the
[2] VENC_CLOCK_MODE register bit:
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In the case of clock mode 1, the
[3] VENC_CLOCK_4X_ENABLE bit is used to control
clock gating.
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In the case of clock mode 0, the VENC_CLOCK_4X_ENABLE bit must be set to 0x1 by software.
NOTE:
After reset, clock mode 0 is selected by default, and the DSS_TV_CLK clock is disabled.
The DSS_TV_CLK / 4 in mode 0, or the DSS_TV_CLK / 2 in mode 1, is used in the DISPC
module to send data to the video encoder.
NOTE:
Clock mode 1 can be used for power-saving purposes, or if a 27-MHz external clock is
provided to the video encoder.
DSS_TV_FCLK can be adjusted depending on the DPLL4 input clock frequency by setting the
PRCM.CM_CLKSEL_DSS[12:8] CLKSEL_TV bit field. If the DPLL4 is selected, the DSS_TV_FCLK is
provided by the DPLL4_ALWON_FCLKOUTM3X2 clock.
NOTE:
If the DSS_TV_FCLK is not provided by DPLL4 but rather by the sys_alt_clk pin, an
external clock generator must be connected to this pin. In this case, a 54-MHz clock is
needed for PAL or NTSC 601, a 49.09-MHz clock is needed for NTSC square pixel, and a
59-MHz clock is needed for PAL square pixel.
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Video DAC stage clocks
The video DAC stage uses one distinct clock: The DSS_TV_FCLK. The video data are latched on the
positive edge of the DSS_TV_FCLK clock.
7.3.1.2
Resets
7.3.1.2.1 Hardware Reset
The display subsystem receives its reset signal DSS_RST (the reset signal of the display subsystem
[DSS] power domain) from the PRCM module.
7.3.1.2.2 Software Reset
The display subsystem can receive a software reset propagated through all of the submodules and used
to initialize the display subsystem. To apply the reset, write to the DSS.
SOFTRESET bit (1: Reset; 0: Normal). The DSS.
[0] RESETDONE bit indicates that the
software reset is complete when its value is 1.
1622
Display Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
