Public Version
Display Subsystem Register Manual
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7.7.2 Display Subsystem Register Descriptions
7.7.2.1
Display Subsystem Registers
Table 7-126. DSS_REVISIONNUMBER
Address Offset
0x000
Physical address
0x4805 0000
Instance
DISS
Description
This register contains the display subsystem revision number.
Type
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
REV
Bits
Field Name
Description
Type
Reset
31:8
Reserved
Read returns 0.
R
0x000000
7:0
REV
Revision number
R
TI internal data
[7:4] Major revision
[3:0] Minor revision
Table 7-127. Register Call Summary for Register DSS_REVISIONNUMBER
Display Subsystem Register Manual
•
Display Subsystem Register Mapping Summary
Table 7-128. DSS_SYSCONFIG
Address Offset
0x010
Physical address
0x4805 0010
Instance
DISS
Description
This register controls the various parameters of the interconnect interface.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
AUTOIDLE
SOFTRESET
Bits
Field Name
Description
Type
Reset
31:5
Reserved
Write 0s for future compatibility. Reads return zero.
RW
0x00000000
4:3
Reserved
Reserved. Keep at reset value.
RW
0x0
2
Reserved
Write 0s for future compatibility . Reads return zero.
RW
0
1
SOFTRESET
Software reset. Set this bit to 1 to trigger a module reset. The bit is
RW
0
automatically reset by the hardware. During reads, it always returns
0.
0x0:
Normal mode
0x1:
The module is reset
0
AUTOIDLE
Enable power management capability
RW
1
0x0:
OCP clock is free-running
0x1:
Automatic OCP clock gating strategy is applied based on
the OCP interface activity
1818
Display Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated