Public Version
Display Subsystem Register Manual
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summarizes the display subsystem instance.
Table 7-116. Display Subsystem Instance Summary
Module Name
Base Address
Size
DSI Protocol Engine
0x4804 FC00
512 bytes
DSI_PHY
0x4804 FE00
64 bytes
DSI PLL Controller
0x4804 FF00
32 bytes
Display Subsystem
0x4805 0000
512 bytes
Display Controller
0x4805 0400
1KB
Display Controller VID1
0x4805 0400
1KB
Display Controller VID2
0x4805 0400
1KB
RFBI
0x4805 0800
256 bytes
Video Encoder
0x4805 0C00
256 bytes
7.7.1 Display Subsystem Register Mapping Summary
7.7.1.1
Display Subsystem Register Mapping Summary
Table 7-117. Display Subsystem Register Mapping Summary
Register Name
Type
Register Width
Address Offset
Physical Address
(Bits)
R
32
0x000
0x4805 0000
RW
32
0x010
0x4805 0010
R
32
0x014
0x4805 0014
R
32
0x018
0x4805 0018
RW
32
0x040
0x4805 0040
R
32
0x05C
0x4805 005C
7.7.1.2
Display Controller Register Mapping Summary
Table 7-118. Display Controller Register Mapping Summary
Register Name
Type
Register Width
Address Offset
Physical Address
(Bits)
R
32
0x000
0x4805 0400
RW
32
0x010
0x4805 0410
R
32
0x014
0x4805 0414
RW
32
0x018
0x4805 0418
RW
32
0x01C
0x4805 041C
RW
32
0x040
0x4805 0440
RW
32
0x044
0x4805 0444
RW
32
0x04C+(m * 0x04)
(1)
0x4805 044C+(m *
0x04)
(1)
RW
32
0x054+(m * 0x04)
(1)
0x4805 0454+(m *
0x04)
(1)
R
32
0x05C
0x4805 045C
RW
32
0x060
0x4805 0460
RW
32
0x064
0x4805 0464
RW
32
0x068
0x4805 0468
RW
32
0x06C
0x4805 046C
RW
32
0x070
0x4805 0470
(1)
m = 0 to 1
1812Display Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated