Public Version
Display Subsystem Register Manual
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Bits
Field Name
Description
Type
Reset
7
DSS_DSI_CLK1_
DSS1_ALWON_FCLK clock selection status (DSI mux)
R
0
STATUS
Indicates if the DSI protocol engine is running from the
DSS1_ALWON_FCLK clock
Read 0: DSS1_ALWON_FCLK is not selected (unused by DSI).
Read 1: DSS1_ALWON_FCLK is selected (used by DSI).
6:2
RESERVED
RESERVED
R
0
1
DSI_PLL_CLK1_
DSI1_PLL_FCLK clock selection status (DISPC mux) Indicates if
R
0
STATUS
the display controller is running from the DSI1_PLL_FCLK clock
Read 0: DSI1_PLL_FCLK is not selected (unused by DISPC).
Read 1: DSI1_PLL_FCLK is selected (used by DISPC).
0
DSS_DISPC_CLK1_
DSS1_ALWON_FCLK clock selection status (DISPC mux)
R
1
STATUS
Indicates if the display controller is running from the
DSS1_ALWON_FCLK clock
Read 0: DSS1_ALWON_FCLK is not selected (unused by
DISPC).
Read 1: DSS1_ALWON_FCLK is selected (used by DISPC).
Table 7-137. Register Call Summary for Register DSS_CLK_STATUS
Display Subsystem Register Manual
•
Display Subsystem Register Mapping Summary
7.7.2.2
Display Controller Registers
Table 7-138. DISPC_REVISION
Address Offset
0x000
Physical address
0x4805 0400
Instance
DISC
Description
This register contains the IP revision code.
Type
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
REV
Bits
Field Name
Description
Type
Reset
31:8
Reserved
Write 0s for future compatibility. Read returns 0.
R
0x000000
7:0
REV
IP revision
R
TI internal data
[7:4] Major revision
[3:0] Minor revision
Table 7-139. Register Call Summary for Register DISPC_REVISION
Display Subsystem Register Manual
•
Display Controller Register Mapping Summary
:
Table 7-140. DISPC_SYSCONFIG
Address Offset
0x010
Physical address
0x4805 0410
Instance
DISC
Description
This register allows the control of various parameters of the interconnect interface.
Type
RW
1822
Display Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated