Public Version
www.ti.com
Display Subsystem Register Manual
Bits
Field Name
Description
Type
Reset
Write 0x0:
VSYNC status bit unchanged
Read 0x1:
VSYNC is true (pending).
Write 0x1:
VSYNC status bit reset
0
FRAMEDONE
FrameDone
RW
0
Read 0x0:
FrameDone is false.
Write 0x0:
FrameDone status bit unchanged
Read 0x1:
FrameDone is true (pending).
Write 0x1:
FrameDone status bit reset
Table 7-145. Register Call Summary for Register DISPC_IRQSTATUS
Display Subsystem Integration
•
Display Subsystem Basic Programming Model
•
•
Display Controller Configuration
:
•
TV Set-Specific Control Registers
•
Video Encoder Programming Sequence
Display Subsystem Register Manual
•
Display Controller Register Mapping Summary
:
•
Table 7-146. DISPC_IRQENABLE
Address Offset
0x01C
Physical address
0x4805 041C
Instance
DISC
Description
This register allows the masking/unmasking of module internal interrupt sources, on an event-by-event basis.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
VSYNC
WAKEUP
SYNCLOST
OCPERROR
FRAMEMASK
EVSYNC_ODD
EVSYNC_EVEN
GFXENDWINDOW
VID2ENDWINDOW
ENDVID1WINDOW
SYNCLOSTDIGITAL
GFXFIFOUNDERFLOW
VID2FIFOUNDERFLOW
VID1FIFOUNDERFLOW
PALETTEGAMMAMASK
ACBIASCOUNTSTATUS
PROGRAMMEDLINENUMBER
Bits
Field Name
Description
Type
Reset
31:17
Reserved
Write 0s for future compatibility. Read returns 0.
RW
0x0000
16
WAKEUP
Wakeup mask
RW
0
0x0:
Wakeup is masked.
0x1:
Wakeup generates an interrupt when it occurs.
15
SYNCLOSTDIGITAL
SyncLostDigital
RW
0
0x0:
SyncLostDigital is masked.
0x1:
SyncLostDigital generates an interrupt when it occurs.
14
SYNCLOST
SyncLost
RW
0
0x0:
SyncLost is masked.
0x1:
SyncLost generates an interrupt when it occurs.
1827
SWPU177N – December 2009 – Revised November 2010
Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated