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Display Subsystem Basic Programming Model
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Table 7-47. Shadow Registers (continued)
Shadow Register Name
Updated on VFP Start Period
Updated on External VSYNC
(LCD output)
(Digital output)
DSS.
(l = 0,1)
X
X
DSS.
(i = 0 to 7)
X
X
DSS.
(i = 0 to 7)
X
X
DSS.
(i = 0 to 7)
X
X
DSS.DISPC_VIDn_CONV_COEFi (i = 0 to 4)
X
X
DSS.
X
X
DSS.
(k = 0 to 3)
X
7.5.3.1
Display Controller Configuration
The following registers define the display controller configuration:
•
DSS.
•
DSS.
•
DSS.
•
DSS.
7.5.3.2
Graphics Layer Configuration
The graphics layer configuration is common to the LCD and the TV set.
7.5.3.2.1 Graphics DMA Registers
The following registers define the graphics DMA engine configuration:
•
DSS.
•
DSS.
•
DSS.
•
DSS.
•
DSS.
•
DSS.
•
DSS.
The following fields define the attributes of the graphics DMA engine:
•
Graphics layer enable (DSS.
[0] GFXENABLE bit): The default value of this
bit at reset time is 0x0 (Disabled). The graphics DMA engine fetches encoded pixels from the system
memory only when the graphics layer is enabled (a valid configuration is programmed for the graphics
layer). The graphics window is present and the graphics pipeline is active.
•
Burst size (DSS.
[7:6] GFXBURSTSIZE field): The default burst size at
reset time is 4 x 32 bytes. The possible values are 4 x 32, 8 x 32, and 16 x 32 bytes. The burst size is
initialized at boot time by the software and never changes as long as the display controller is enabled.
This field indicates the maximum burst size for the specific pipeline. In case of misalignment, the DMA
engine may issue single and/or smaller burst requests because the burst size must be aligned to the
burst boundary.
•
Preload configuration (DSS.
[11] GFXFIFOPRELOAD bit): The default
preload configuration uses the DSS.
register value (the reset value is 256
bytes) to define the number of bytes to be fetched from system memory into the display controller
graphics FIFO. By programming the DSS.
[11] GFXFIFOPRELOAD bit,
software users select between preload register (with 256 bytes as the reset value) and the high
threshold value for preload of the encoded pixels. For best performance, the configuration of
thresholds is defined using the FIFO size (in bytes) minus 1 for the high threshold, and the FIFO size
(in bytes) minus the burst size (in bytes) for the low threshold, which provides 960, 992, and 1008,
respectively, for burst sizes 16x32, 8x32, and 4x32. Note also that the preload value is defined based
on the following display types:
1708
Display Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
