Texas Instruments OMAP36 Series, Technical Reference Manual

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Display Subsystem Register Manual
Bits Field Name Description Type Reset
10:0 PPL Pixels per line RW 0x000
Encoded value (from 1 to 2048) to specify the number of pixels contains
within each line on the display (program to value minus one). When
running in normal mode (stall mode is bypassed by setting
DSS.
DISPC_CONTROL [11] STALLMODE =0) the line width must be set
to a value multiple of 8 pixels (ex: PPL=0x7)
Table 7-173. Register Call Summary for Register DISPC_SIZE_LCD
Display Subsystem Environment
• Transaction Timing Diagrams : [0] [1]
Display Subsystem Functional Description
• Up-/Down-Sampling : [2]
Display Subsystem Basic Programming Model
• Display Controller Basic Programming Model : [3]
• LCD-Specific Control Registers : [4]
• LCD Attributes : [5] [6]
• LCD Timings : [7] [8]
Display Subsystem Use Cases and Tips
• Configure DISPC Timing, Window, and Color : [9]
• Configure DISPC Timing, Window, and Color : [10] [11]
Display Subsystem Register Manual
• Display Controller Register Mapping Summary : [12]
Table 7-174. DISPC_GFX_BAj
Address Offset 0x080 + j * 0x04 Index j = 0 to 1
Physical address 0x4805 0480+ j * 0x04 Instance DISC
Description The register configures the base address of the graphics buffer displayed in the graphics window (0 & 1 :for
ping-pong mechanism with external trigger, based on the field polarity, 0 only used when graphics pipeline on the
LCD output and 0 & 1 when on the 24-bit digital output).
Shadow register, updated on VFP start period or EVSYNC.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GFXBA
Bits Field Name Description Type Reset
31:0 GFXBA Graphics base address RW 0x00000000
Base address of the graphics buffer (aligned on pixel size boundary)
(in case 1-, 2-, and 4-BPP, byte alignment is required)
Table 7-175. Register Call Summary for Register DISPC_GFX_BAj
Display Subsystem Basic Programming Model
• Display Controller Basic Programming Model : [0]
• Graphics DMA Registers : [1] [2]
• Rotation/Mirroring Registers : [3]
Display Subsystem Register Manual
• Display Controller Register Mapping Summary : [4]
1843 SWPU177N – December 2009 – Revised November 2010 Display Subsystem
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