VIDZSIZEX
SIZE
VIDn
DISPC
PLL
LCD
SIZE
DISPC
ratio
h
]
0
:
10
[
_
_
]
0
:
10
[
_
_
_
=
VIDSIZEY
SIZE
VIDn
DISPC
Y
VIDORGSIZE
SIZE
PICTURE
VIDn
DISPC
ratio
v
]
0
:
10
[
_
_
]
0
:
10
[
_
_
_
_
=
ratio
h
ratio
v
PCD
_
2
_
min
´
=
2
_
1
£
<
ratio
v
)
)
1
_
(
2
2
_
,
_
2
_
max(
min
-
´
-
´
=
ratio
h
ratio
v
ratio
h
ratio
v
PCD
4
_
2
£
<
ratio
v
dss-E103
Public Version
Display Subsystem Basic Programming Model
www.ti.com
Figure 7-126. PCDmin Formulas (V Down-Sampling Only)
The PCDmin for horizontal downsampling only is defined by the following formula:
While downsampling by n, PCDmin = n
For H+V downsampling, the formula is the following:
PCDmin = max(PCDmin H only, PCDmin V only) as defined above
The refresh rate depends on the following parameters:
•
Horizontal front porch (the DSS.
[19:8] HFP bit field)
•
Horizontal back porch (the DSS.
[31:20] HBP bit field)
•
Horizontal synchronization pulse width (the DSS.
[7:0] HSW bit field)
•
Vertical front porch (the DSS.
[19:8] VFP bit field)
•
Vertical back porch (the DSS.
[31:20] VBP bit field)
•
Vertical synchronization pulse width (the DSS.
[7:0] VSW bit field)
•
Number of lines per panel (the DSS.
[26:16] LPP bit field)
•
Number of pixels per line (the DSS.
[10:0] PPL bit field)
•
4- or 8-bit interface for the passive matrix monochrome panel (the DSS.
[4] M8B bit)
The following bit fields define the behavior of the internal blocks:
•
Spatial/temporal dithering logic enabled (DSS.
[7]
SPATIALTEMPORALDITHERENABLE bit)
•
Spatial/temporal dithering logic number of frames (DSS.
SPATIALTEMPORALDITHERFRAMES bit field). The default value of this bit field at reset time is 0x0,
which is 1 frame only (spatial processing without temporal dithering). The possible values are 0x0 (one
frame), 0x1 (two frames), and 0x2 (four frames). The number of frames is initialized before enabling
the spatial/temporal dithering unit. The software must not change this bit field value while the
spatial/temporal unit is enabled.
The following bit field defines the clock gating strategy:
•
In active matrix mode, the pixel clock is always gated or only when valid data are present (the
DSS.
[0] PIXELGATED bit).
7.5.3.5.3 LCD Overlay
The following bit fields define the overlay attributes of the LCD output:
•
Transparency color key (the DSS.DISPC_TRANS_COLOR0i register (i = 0))
•
Transparency color key enable (the DSS.
[10] TCKLCDENABLE bit)
•
Transparency color key selection between the destination graphics transparency color key and the
source video transparency color key (the DSS.
[11] TCKLCDSELECTION bit)
•
The default solid background color is defined in the DSS.
DEFAULTCOLOR bit field (i=0).
•
Alpha blender Enable (DSS.
[18] LCDALPHABLENDERENABLE)
•
Global alpha blending values (DSS.
[23:16] VID2GLOBALALPHA and
DSS.
[7:0] GFXGLOBALALPHA). The value 0xFF corresponds to 100%
opaque and 0 to 100% transparent
1732
Display Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated