Texas Instruments OMAP36 Series, Technical Reference Manual

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Display Subsystem Register Manual
Table 7-150. DISPC_CONFIG
Address Offset 0x044
Physical address 0x4805 0444 Instance DISC
Description This control register configures the display controller module.
Shadow register, updated on VFP start period or EVSYNC
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
CPR
LOADMODE
FIFOMERGE
FIFOFILLING
FUNCGATED
PIXELGATED
VSYNCGATED
HSYNCGATED
ACBIASGATED
TCKDIGENABLE
TCKLCDENABLE
FIFOHANDCHECK
PIXELDATAGATED
TCKDIGSELECTION
TCKLCDSELECTION
PIXELCLOCKGATED
PALETTEGAMMATABLE
TVALPHABLENDERENABLE
LCDALPHABLENDERENABLE
Bits Field Name Description Type Reset
31: 20 Reserved Write 0s for future compatibility. Read returns 0 RW 0x00000
19 TVALPHABLENDER Selects the alpha blender (TV output) RW 0
ENABLE
0x0: Alpha blender is disabled.
0x1: The alpha blender is enabled.
18 LCDALPHABLENDER Selects the alpha blender (LCD output) RW 0
ENABLE
0x0: Alpha blender is disabled.
0x1: The alpha blender is enabled.
17 FIFOFILLING Controls if the FIFO are refilled only when the LOW threshold is RW 0
reached or if all FIFO are refilled when at least one of them
reaches the LOW threshold.
0x0: Each FIFO is refilled when it reaches LOW threshold.
0x1: All FIFOs are refilled up to high threshold when at least
one of them reaches the LOW threshold. (only active
FIFOs should be considered and when reaching the end
of the frame the FIFO goes to empty condition so no
need to fill it again).
16 FIFOHANDCHECK Controls the handshake between FIFO and RFBI STALL to RW 0
prevent from underflow. The bit should be set to 0 when the
module is not in STALL mode.
0x0: Only the STALL signal from RFBI is used regardless of
the FIFO fullness information to provide data to the
RFBI module.
0x1: The STALL signal from RFBI is used in combination
with the FIFO fullness information to provide data to the
RFBI module only when it does not generated FIFO
underflow.
15 CPR Color phase rotation control wr: VFP RW 0
0x0: Color phase rotation disabled
0x1: Color phase rotation enabled
14 FIFOMERGE FIFO merge control RW 0
wr: EVSYNC or VFP
0x0: FIFO merge disabled
Each FIFO is dedicated to one pipeline.
1833 SWPU177N – December 2009 – Revised November 2010 Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated